Simulation and investigation of parameters affecting the reduction of power consumption in multiplication circuits using CNT transistor technology
Subject Areas : Electronics Engineeringabdolrasoul moghateli 1 , hosssein momenzadeh 2 , Mohammad Nader Kakai 3
1 - Graduate student of Bushehr Branch of Azad University
2 - faculty members of Bushehr Branch of Azad University
3 - faculty members of Bushehr Branch of Azad University
Keywords:
Abstract :
Analog multipliers are useful blocks used in implementing functions such as automatic control, modulation, detectors, adaptive filters, and neural networks. In this paper, we present a new four-quadratic analog multiplier based on carbon nanotube transistors. Newly designed current square circuits and a current mirror, all operating at low voltage (1V), are essential components in realizing mathematical equations. The multiplier circuit is designed using CNTFET technology, 32 nm, and the multiplier provided in the HSPICE simulator is simulated to validate the circuit performance. The simulation results showed that the circuit has the desired performance up to a frequency of 2 GHz and shows a maximum power consumption of 3.7464uw and also has a THD of 0.226043%.
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[8] F. Pr´egaldiny, J. Baptiste Kammerer , C. Lallement,” Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design”, in proc. 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 4244-0395.
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[25] A.Ravindran, K.Ramarao, E.Vidal, M.Ismail, “Compact low voltage four quadrant CMOS current multiplier,” Electron Lett, vol. 37, no. 24, pp. 1428–9, 2001.
[26] P.Prommee, M. Somdunyakanok, M. Kumngern, K. Dejhan, “Single low-supply current-mode CMOS analog multiplier circuit,” in proc.IEEE International Sym-posium on Communications and Information Technologies, ISCIT. 2006. pp. 1101–4.
[27] V. Oliveira, N.Oki, “Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process, ” In proc International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007. pp. 52–5.
[28] N. Beyraghi, A. Khoei, “CMOS design of a low power and high precision four-quadrant analog multiplier,” AEU - International Journal of Electronics and Communications, vol. 63, no. 1, pp.400-7, 2015.
_||_[1] YK. Seng, SS. Rofail, “Design and analysis ofa ±1 V CMOS foµr-qµadrant analogµemµltiplier,” in Proc. IEEE Circµits Dev Syst, 1998.
[2] T. Suzuki, T. Oura, T. Yoneyama, H. Asai, “A new CMOS 4Q-multiplier using linearand saturation regions complementally,”InProc. of solid-state circuitsconference (ESSCIRC), 2002.
[3] K Tanno, O. Ishizuka, Z. Tang, “Four-quadrant CMOS current-mode multiplierindependent ofdevice parameters, ” IEEE Trans Circuit Syst II, vol.47,no 5, pp. 473–7, 2000.
[4] A. Naderi, A. Khoei, K. Hadidi, H.Ghasemzadeh, “A new high speed and low powerfour-quadrant CMOS analog multiplier in current-mode,” AEu – Int J ElectronCommun , vol. 63, no. 9, pp. 769–75, 2009.
[5] A. J. Lopez-Martin, A. Carlosena, “Current-modemultiplier/divider circuits basedon the MOS translinear principle,” Analog Integr CircuitsSignal Process, 2001.
[6] A. J. Lopez-Martin, C.A. De La Cruz Bias, J. Ramirez-Angulo, R.G. Carvajal, “Compact low-voltage CMOS current-mode multiplier/divider, ” In Proc. IEEE international symposium on circuits and systems (ISCAS), 2010. pp. 1583–6.
[7] J.Antonio Lopez-Marti, C. A. De La Cruz Blas, J. Ramirez-Angulo, R.G.Carvajal, “Current-Mode CMOS Multiplier/Divider Circuit Operating in Linear/Saturation Regions,” Analog Integr Circ Sig Process,” vol. 66 , no 10, pp. 299-302, 2010.
[8] F. Pr´egaldiny, J. Baptiste Kammerer , C. Lallement,” Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design”, in proc. 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 4244-0395.
[9] L. mao peng , Z. zhang ,s. wang, “Carbon Nanotube Electronics Recent Advances,” in J Materialstoday, vol.17, no. 9, pp.433-442, November 2014 .
[10] I. Makwana, V. Sheth, “A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 Nnmcnfet Technology,” International Journal of VLSI design &Communication Systems (VLSICS), vol. 3, no. 2, pp. 73-83, April 2012.
[11] Y.Bin. Kim, “Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor,” Iransactions on Electrical and Electronic Materials, vol. 12, no. 5, pp. 175-188 , October 2011.
[12] Rodney S.Ruoff, DongQian, WingKam Liu, C.R.Physique, 4, 2003, 993
[13] H. Raffi-Tabar, Physics Reports, 390, 2004, 235.
[14] R.Satio, M. S. Dresselhaus, G. Dresselhaus, “Physical Properties Of Carbon Nanotubes,” Imperial College Press ISBN 1-86094-093-5, 1998.
[15] J. Peder Dahl, “Introduction to the Quantum World of Atoms and Molecules, ” World Scientific Publishing Company, 9810245653, 2001.
[16] M.H. Hashiesh, S.A. Mahmoud, A.M.Soliman, “New four-quadrant CMOS currentmode and voltage-mode multipliers, Analog Integr Circuits Signal Process, vol. 45, no 3, pp. 295–307, 2005.
[17] S. Minaei, E.Yuce, “New squarer circuits and a current-mode full-wave rectifier topology suitable for integration,” in J Radio Eng, vol. 19,no. 4 pp. 657–61, 2010.
[18] R.Hidayat, K.Dejhan, P.Moungnoul, Y.Miyanaga, “A GHz simple CMOS squarercircuit, ” in proc. IEEE International Symposium on Communications and Information Technologies (ISCIT), 2008, pp. 539–42.
[19] K.M. Al-Tamimi, M. A.Al-Absi, “An ultra-low power high accuracy current-mode CMOS squaring circuit,” In proc. International Conference ofElectrical and Electronics Engineering, 2012. pp. 872–4.
[20] S. Wisetphanichkij, N.Singkrajom, M.Kumngern, K.Dejhan, “A low-voltage CMOS current squarer circuit. ” in proc. IEEE International Symposium on Communications and Information Technology (ISCIT), 2005, pp. 271–4.
[21] M.H. Danesh, E. Mahmoudian, A.Emami Fard ” A new current-mode squarer circuit for RMS-to-DC converter,” Int J Eng Innovative Technol (IJEIT) , vol.3, no. 2, 2013
[22] M. Kumngern, K. Dejhan, “Versatile dual-mode class-AB four-quadrant analog multiplier,” Int J Signal Process, vol. 2, no. 4, 2005.
[23] C.A.De La Cruz-Blas, A.J.Lopez-Martin, A.Carlosena, “1.5 V four-quadrant CMOS current multiplier/divider,” Electron Lett, vol. 39, no. 5, pp. 434–6, 2003.
[24] C. Popa, “Improved accuracy current-mode multiplier circuits with applications in analog signal processing,” IEEE Trans Very Large Scale Integr (VLSI) Syst, vol.22, no. 2, pp. 443–7, 2014.
[25] A.Ravindran, K.Ramarao, E.Vidal, M.Ismail, “Compact low voltage four quadrant CMOS current multiplier,” Electron Lett, vol. 37, no. 24, pp. 1428–9, 2001.
[26] P.Prommee, M. Somdunyakanok, M. Kumngern, K. Dejhan, “Single low-supply current-mode CMOS analog multiplier circuit,” in proc.IEEE International Sym-posium on Communications and Information Technologies, ISCIT. 2006. pp. 1101–4.
[27] V. Oliveira, N.Oki, “Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process, ” In proc International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007. pp. 52–5.
[28] N. Beyraghi, A. Khoei, “CMOS design of a low power and high precision four-quadrant analog multiplier,” AEU - International Journal of Electronics and Communications, vol. 63, no. 1, pp.400-7, 2015.
