Nano-photonic chip network
Subject Areas : Electronics Engineering
Mohammad Amir
Ghasemi Shabankareh
1
(Pasargad University of Shiraz, undergraduate student of Telecommunications, Shiraz, Wolfajr Town)
Sara
Rahimi Javanmardi
2
(Iran University of Applied Sciences, Telecommunication Industries, Shiraz)
Keywords:
Abstract :
Chip communication, including short correlation, multi-dominant, critical delay correlation, synchronization messages, long data transmission, single format with sensitive passability; Limits the power efficiency and performance of multi-core multi-processor systems. This paper deals with a low-power, high-performance nano-photonic chip network compatible with CMOS; This category is called Iris. The Iris subnet, which is based on linear waveguides and is optimized for throughput and connected in orbit, supports data transmission with sensitive throughput. Also, the Iris subnet, which operates on a surface (two-way) waveguide as well as WDm and has several broad domains, improves critical latency traffic and supports orbital communications. Overall, the proposed design offers a chip connection with high power efficiency, low latency and excellent throughput.
