Improvement of SNDR using Optimization of Feedback Path Coefficients for Second Order CRFB Modulators in Sigma-Delta Analog to Digital Converters
Subject Areas : Electronics Engineering
Maryam Shahriary
1
,
Abdolrasool Ghasemi
2
,
najmeh cheraghi shirazi
3
1 - department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran
2 - department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran
3 - department of electrical engineering, bushehr branch, islamic azad university, bushehr, iran
Keywords: CRFB structure, Analog to Digital Converter, operational amplifiers, sigma-delta converters, optimization of feedback coefficients,
Abstract :
Analog to digital converters are divided into two categories, Nyquist rate converter and oversampling converter, in terms of sampling frequency. At oversampling converter, input signal are sampled at several times the Nyquist rate. Increasing the over sampling rate leads to an increase in effective resolution, but although the use of high sampling rate for wide band signals is impractical due to the need for high sampling frequency and power consumption. Increasing the number of bits also increases the dynamic range as opposed to the multi-bit DAC required in the linear feedback path. In this paper, we designed sigma delta structure with 12 bit resolution, 1-v power supply for low power applications. on the other hand, increasing levels of quantization(number of bits) causes the reduction in-band noise power of the system, as well as the modulator stability improves without need increasing oversampling ratio. The maximum value of a signal-to-noise-and-distortion ratio(SNDR) will be achieved by means of choosing appropriate feedback coefficients. Simulation results of a 12-bit,2.4-MS/s , and 1-v proposed structure in a 0.18-µm CMOS technology show a signal-to-noise-and-distortion ratio (SNDR) of 71.3 dB, a power consumption of 451µW, and figure of merit 3.76(pJ/Conver.step.)
[1] S. Northworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters, IEEE Press, Piscataway, NJ, 1997.
[2] A. marques¸ V.zopelso¸ M.steyaert and m.sansen ¸ “Transaction on Circuits and systems-ll,” IEEE Analog and Digital signal processing, vol.45 , no.9 , Sep. 1998.
[3] F. Cannillo et al., “1.4 V 13 W 83 dB DR CT- modulator with dual-slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. IEEE Eur. Solid-State Circuits, 2011, pp. 267–270..
[4] L. Liu, Dongmei Li, L. Chen, Yafei Ye, and Z.Wang, “ A 1-V 15-Bit Audio -ADC in 0.18µm CMOS ,” IEEE transaction on circuits and system—i: regular papers, vol. 59, no. 5, pp. 510 – 513, May 2012.
[5] Y. Yoon, and et al, “A Delta–Sigma Modulator for Low-Power Analog Front Ends in Biomedical Instrumentation,” IEEE Transactions on Instrumentation and Measurement, vol. 65, no. 7, pp. 1530-1539, 2016.
[6] J. Johansson et al., “A 16-bit 60μW Multi-Bit ΣΔ Modulator for Portable ECG Applications,” Proc. 29th European Solid-State Circuits Conference, 2003, pp. 161 – 164.
[7] H. Lee, and et al, “A Compressive Sensing-Based CMOS Image Sensor With Second-Order ADCs,” IEEE Sensors Journal, vol. 18, no. 6, pp. 2404-2409, Mar. 2018.
[8[ H. Park, K. Nam, K Su, K. Vleugels, and B A. Wooley, “A 0.7-V 870-uw Digital-Audio CMOS Sigma-Delta Modulator,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 218 – 21, Apl. 2009
[9] S. T. Chandrasekaran, V. E. G. Karnam and A. Sanyal, “0.36-mW, 52-Mbps True Random Number Generator Based on a Stochastic Delta–Sigma Modulator, ” IEEE Solid-State Circuits Letters, vol. 3, pp. 190-193, 2020.
[10] J. Goes, B. Vaz, R. Monteiro, and Paulino, “A 0.9 V modulator with 80 dB SNDR and 83 dB DR using a single-phase technique,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2006, pp. 74–75.
[11] B. Tran and C. Huynh, “A 12-Bit 33-mW and 96-MHz Discrete-Time Sigma Delta ADC in 130 nm CMOS Technology, ” International Symposium on Electrical and Electronics Engineering (ISEE), 2019, pp. 1-6.
_||_[1] S. Northworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters, IEEE Press, Piscataway, NJ, 1997.
[2] A. marques¸ V.zopelso¸ M.steyaert and m.sansen ¸ “Transaction on Circuits and systems-ll,” IEEE Analog and Digital signal processing, vol.45 , no.9 , Sep. 1998.
[3] F. Cannillo et al., “1.4 V 13 W 83 dB DR CT- modulator with dual-slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. IEEE Eur. Solid-State Circuits, 2011, pp. 267–270..
[4] L. Liu, Dongmei Li, L. Chen, Yafei Ye, and Z.Wang, “ A 1-V 15-Bit Audio -ADC in 0.18µm CMOS ,” IEEE transaction on circuits and system—i: regular papers, vol. 59, no. 5, pp. 510 – 513, May 2012.
[5] Y. Yoon, and et al, “A Delta–Sigma Modulator for Low-Power Analog Front Ends in Biomedical Instrumentation,” IEEE Transactions on Instrumentation and Measurement, vol. 65, no. 7, pp. 1530-1539, 2016.
[6] J. Johansson et al., “A 16-bit 60μW Multi-Bit ΣΔ Modulator for Portable ECG Applications,” Proc. 29th European Solid-State Circuits Conference, 2003, pp. 161 – 164.
[7] H. Lee, and et al, “A Compressive Sensing-Based CMOS Image Sensor With Second-Order ADCs,” IEEE Sensors Journal, vol. 18, no. 6, pp. 2404-2409, Mar. 2018.
[8[ H. Park, K. Nam, K Su, K. Vleugels, and B A. Wooley, “A 0.7-V 870-uw Digital-Audio CMOS Sigma-Delta Modulator,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 218 – 21, Apl. 2009
[9] S. T. Chandrasekaran, V. E. G. Karnam and A. Sanyal, “0.36-mW, 52-Mbps True Random Number Generator Based on a Stochastic Delta–Sigma Modulator, ” IEEE Solid-State Circuits Letters, vol. 3, pp. 190-193, 2020.
[10] J. Goes, B. Vaz, R. Monteiro, and Paulino, “A 0.9 V modulator with 80 dB SNDR and 83 dB DR using a single-phase technique,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2006, pp. 74–75.
[11] B. Tran and C. Huynh, “A 12-Bit 33-mW and 96-MHz Discrete-Time Sigma Delta ADC in 130 nm CMOS Technology, ” International Symposium on Electrical and Electronics Engineering (ISEE), 2019, pp. 1-6.
