Optimizing power consumption and delay in designing full adder based on CMOS technology
Subject Areas : Electronic Engineering
Vahid
Dehghan
1
(گروه مهندسی برق، واحدصفاشهر، دانشگاه آزاد اسلامی، صفاشهر، ایران)
Mohsen
Katebi Jahromi
2
(دانشگاه آزاد اسلامی واحد صفاشهر)
Keywords: Characteristic impedance, even-odd mode, Wilkinson power divider,
Abstract :
Abstract: The aim of this article is to investigate the optimization of power consumption and delay in the design of full adder based on CMOS technology. Different ideas that have existed in the implementation of adder circuits have been simulated. In the implementation of the adder cell circuit, in some articles the input classes are different and in some others the output classes are different. In different articles, complementary CMOS logic, ratio, complementary pass transistor, transfer gates and majority function have been used. In this paper, a full adder based on CMOS technology is designed and simulated by HSPICE software. The results show that the optimization of power consumption and delay in the design of the full adder has been done effectively using the proposed method, and the simulation results show the superiority of the proposed adder over other models.
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