Design of an optical receiver limiting amplifier circuit in 0.18 μm CMOS technology up to a bandwidth of about 2.5 GHz
Subject Areas :
1 - Department of Electrical Engineering, Bey. C., Islamic Azad University, Beyza, Iran
Keywords: Optical communication receiver, Transimpedance amplifier, limiting amplifier, Full active design,
Abstract :
One of the challenges ahead in the field of optical communications is the design of transmitter and receiver circuits with submicron CMOS technologies for gigabit/second applications. This challenge becomes more apparent as submicron technologies become smaller and smaller, their parasitic and second-order effects become larger, posing numerous problems for the designer. In the design of optical receivers, two important factors must be considered. These two factors are the amplifier bandwidth and the input sensitivity. The total bandwidth of the optical receiver is usually determined in the Transimpedance Amplifier (TIA) and can be estimated by its time constant, which is due to the parasitic capacitance of the photodiode and the input resistance of the TIA. Since the signal generated in the TIA stage for the photodiode input current level usually has a small amplitude of a few tens of millivolts, one or more other amplifier stages are placed after the TIA stage to provide the appropriate signal swing for the logic levels (clock and data recovery circuits). For this purpose, multiple stages of limiting amplifier (LA) cells are used. A major goal in high-speed systems is to design LA stages with high gain, wide bandwidth, and high output swing. In this article, the main goal of designing the analog part of optical receivers for telecommunication applications is to actively study, investigate, and pay attention to circuits with communication applications, in addition to considering parameters such as appropriate frequency response, low noise immunity of devices, and low power losses
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