A network on the chip is a solution to connection problems compared with traditional-based chip which can fulfil multi-dimensional communication requirements. The router is a key component of the communication network which is referred as its backbone. Since the router occupies the largest area on the chip and it is the most widely used network component, in this paper, the architecture of the router in the network on the chip is examined and its roles with its components and their effect on the performance of the network are investigated, considering the parameters including time (delay), the area and more importantly the power consumption. It is shown that any modification, combination, or correction in any of the component effect on power consumption of the router and hence on the power consumption of the whole chip. To this end, the related works are examined to make an appropriate estimation of their analogy. This article will help researchers who are trying to design an optimal router based on power consumption. تفاصيل المقالة

Abstract:
This paper presents a novel design of a ternary multiplier
based on graphene nanoribbon field-effect transistor
(GNRFET). GNRFET, as a new material with superior
physical and electronic properties, can be a good choice
instead of conventional devices such as metal–oxide–
semiconductor field-effect transistor (MOSFET) and
CNTFET. Moreover, multiple-valued logic (MVL) can
help to reduce area and decrease the computational step
compared with binary logic. We proposed a ternary
multiplier with the resistors to produce ternary logic. The
proposed multiplier performances are analyzed by
evaluating the delay, power, and power-delay product
(PDP), with 15 nm process technologies based on
GNRFET. The simulation results with HSPICE
demonstrate that the proposed design framework
outperforms state-of-the-art designs in circuit parameters. تفاصيل المقالة