Voltage Difference Technique in Junctionless Tunneling FET for Suppression of Ambipolar Conduction

الموضوعات : فصلنامه نانوساختارهای اپتوالکترونیکی

Morteza Rahimian ¹ (Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran)

تاريخ الإرسال : 17 الأربعاء , ذو الحجة, 1444 تاريخ التأكيد : 17 الجمعة , جمادى الأولى, 1445 تاريخ الإصدار : 17 الأربعاء , ربيع الثاني, 1445

الکلمات المفتاحية: Band-to-band tunneling (BTBT), Tunneling barrier width, Off-state current, Ambipolarity, Junctionless TFET, 2D simulation,

ملخص المقالة :

Abstract:
A detailed study of a novel configuration for junctionless tunneling FET (J-TFET) with extremely low off- (I_off) and ambipolar current (I_amb) is reported in this paper. In order to achieve desirable on/off current ratio (I_on/I_off), we have employed voltage difference technique on the gate electrode based on the potential distribution benefits. Main and side gates with an optimum voltage difference creates a stepped potential profile along the channel. This raises the drain side’s bands, reduces the electric field, puts restriction on the flow of charge carriers, and finally remarkable reduction of I_amb from 6.52×10^-10 A/µm to 1.14×10^-17 A/µm. Also an extremely low subthreshold swing (SS) (22 mV/dec) is achieved thanks to the sharp transition from off- to the on-state. Finally we have investigated the electrical performance of the proposed device for sub-30 nm channel length to examine its immunity against short channel effects. Therefore, our approach renders the novel structure more desirable for the future low power applications. 

المصادر:

[1]M. Rahimian and Ali. A. Orouji. Investigation of the electrical and thermal performance of SOI MOSFETs with modified channel engineering. Mater Sci Semicond Process., 16 (5) (Oct. 2013) 1248-1256. Available: https://doi.org/10.1016/j.mssp.2012.12.001

[2]M. Rahimian, Ali. A. Orouji and A. Aminbeidokhti. A novel deep submicron SiGe-on-insulator (SGOI) MOSFET with modified channel band energy for electrical performance improvement. Curr. Appl Phys., 13 (4) (Jun. 2013) 779-784. Available: https://doi.org/10.1016/j.cap.2012.12.005

[3]P. Bahrami, M. R. Shayesteh, M. Pourahmadi, H. Safdarkhani.  Improvement of the Drive Current in 5nm Bulk-FinFET Using Process and Device Simulations. J Opt Nanostructures., 5 (1) (Feb. 2020) 65-81. Available: https://dorl.net/dor/20.1001.1.24237361.2020.5.1.5.0

[4]A. M. Ionescu and H. Riel. Tunnel field-effect transistors as energy efficient electronic switches. Nature., 479 (7373) (Nov. 2011) 329-337. Available: https://doi.org/10.1038/nature10679

[5]W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu. Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Lett., 28 (8) (Aug. 2007) 743–745. Available: https://doi.org/10.1109/LED.2007.901273

[6]M. Roohy, R. Hosseini.  Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor. J Opt Nanostructures., 4 (2) (May. 2019) 13-28. Available: https://dorl.net/dor/20.1001.1.24237361.2019.4.2.2.2

[7]M. A. Eshkalak, R. Faez.  A Computational Study on the Performance of Graphene Nanoribbon Field Effect Transistor. J Opt Nanostructures., 2 (3) (Aug. 2017) 1-12. Available: https://dorl.net/dor/20.1001.1.24237361.2017.2.3.1.9

[8]M. Rahimian and M. Fathipour. Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric. Mater Sci Semicond Process., 63 (1) (Jun. 2017) 142–152. Available: https://doi.org/10.1016/j.mssp.2016.12.011

[9]D. Keighobadi, S. Mohammadi, M. Mohtaram. Recessed Gate Cylindrical Heterostructure TFET, a Device with Extremely Steep Subthreshold Swing. Trans. Electr. Electron. Mater., 23 (Apr. 2021) 81–87. Available: https://doi.org/10.1007/s42341-021-00321-4

[10]G. Musalgaonkar, Sh. Sahay, R. S. Saxena and M. J. Kumar. Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study. IEEE Trans. Electron Devices., 66 (10)  (Oct. 2019) 4425–4432. Available: https://doi.org/10.1109/TED.2019.2933756

[11]M. Rahimian, and M. Fathipour. Asymmetric junctionless nanowire TFET with built-in n⁺ source pocket emphasizing on energy band modification. J. Comput. Electron., 15 (4) (Dec. 2016) 1297–1307. Available: https://doi.org/10.1007/s10825-016-0895-1

[12]Z. Ahangari.  Switching Performance of Nanotube Core-Shell Heterojunction Electrically Doped Junctionless Tunnel Field Effect Transistor. J Opt Nanostructures., 5 (2) (May. 2020) 1-12. Available: https://dorl.net/dor/20.1001.1.24237361.2020.5.2.1.8

[13]M. M. Ghiasvand, Z. Ahangari, H. Nematian.  Performance Optimization of an Electrostatically Doped Staggered Type Heterojunction Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate. J Opt Nanostructures., 7 (1) (Jan. 2022) 19-36. Available: https://doi.org/10.30495/jopn.2022.29617.1249

[14]M. K. Anvarifard, Ali A. Orouji. Energy Band Adjustment in a Reliable Novel Charge Plasma SiGe Source TFET to Intensify the BTBT Rate. IEEE Trans. Electron Devices., 68 (10) (Oct. 2021) 5284–5290. Available: https://doi.org/10.1109/TED.2021.3106891

[15]M. Rahimian, and M. Fathipour. Junctionless nanowire TFET with built-in n-p-n bipolar action: physics and operational principle. J. Appl. Phys., 120 (22) (Nov. 2016) 225702. Available: https://doi.org/10.1063/1.4971345

[16]R. M. Imen Abadi, S. Ali S. Ziabari. Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications. Microelectron. Eng., 162 (16) (Aug. 2016) 12-16. Available: https://doi.org/10.1016/j.mee.2016.04.016

[17]M. Rahimian.  Controlling Ambipolar Current in a Junctionless Tunneling FET Emphasizing on Depletion Region Extension. J Opt Nanostructures., 8 (1) (Jan. 2023) 13-31. Available: https://doi.org/10.30495/jopn.2023.31255.1274

[18]Sh. Sahay and M. J. Kumar, Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX. IEEE Trans. Electron Devices, 62 (11) (Nov. 2015) 3882–3886. Available: https://doi.org/10.1109/TED.2015.2478955

[19]D. B. Abdi and M. J. Kumar, Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain. IEEE J. Electron Devices Soc, 2 (6) (Nov. 2014) 187–190. Available: https://doi.org/10.1109/JEDS.2014.2327626

[20]M. Aslam, G. Korram, D. Sharma, Sh. Yadav, N. Sharma, Enhancement of the DC performance of a PNPN hetero‑dielectric BOX tunnel field‑effect transistor for low‑power applications. J. Comput. Electron, 19 (Dec. 2019) 271–276. Available: https://doi.org/10.1007/s10825-019-01427-y

[21]S. Kumar, B. Raj, B. Raj, Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design. Silicon, 13 (Jun. 2020) 1599–1607. Available: https://doi.org/10.1007/s12633-020-00547-6

[22]S. Zafar, M. A. Raushan, Sh. Ahmad, M. J. Siddiqui, Reducing off-state leakage current in dopingless transistor employing dual metal drain. Semicond. Sci. Technol, 35 (1) (Dec. 2019). Available: https://doi.org/10.1088/1361-6641/ab542b

[23]N. Damrongplasit, S. H. Kim, and T. J. K. Liu, Study of Random Dopant Fluctuation Induced Variability in the Raised-Ge-Source TFET. IEEE Electron Device Lett, 34 (2) (Feb. 2013) 184-186. Available: https://doi.org/10.1109/LED.2012.2235404

[24]N. Damrongplasit, Ch. Shin, S. H. Kim, R. A. Vega and T. J. K. Liu, Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs. IEEE Trans. Electron Devices, 58 (10) (Oct. 2011) 3541–3548. Available: https://doi.org/10.1109/TED.2011.2161990

[25]B. Ghosh and M. W. Akram, Junctionless Tunnel Field Effect Transistor. IEEE Electron Device Lett, 34 (5) (May. 2013) 584–586. Available: https://doi.org/10.1109/LED.2013.2253752

[26]M. J. Kumar and S. Janardhanan, Doping-Less Tunnel Field Effect Transistor: Design and Investigation. IEEE Trans. Electron Devices, 60 (10) (Oct. 2013) 3285–3290. Available: https://doi.org/10.1109/TED.2013.2276888

[27]J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, Nanowire transistors without junctions. Nature Nanotechnol, 5 (3) (Mar. 2010) 225–229. Available: https://doi.org/10.1038/nnano.2010.15

[28]E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, Theory of the Junctionless Nanowire FET. IEEE Trans. Electron Devices, 58 (9) (Sep. 2011) 2903–2910. Available: https://doi.org/10.1109/TED.2011.2159608

[29]C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, Junctionless multigate field-effect transistor. Appl. Phys. Lett. 94 (5) (Jan. 2009) 53511-53513. Available: https://doi.org/10.1063/1.3079411

[30]M. Bolokian, Ali. A. Orouji, A. Abbasi, M. Houshmand.  Pyramid P⁺ area in SOI junction-less MOSFET for logic applications: DC investigation. Appl. Nanosci., (Feb. 2023). Available: https://doi.org/10.1007/s13204-023-02808-3

[31]M. Bolokian, Ali. A. Orouji, A. Abbasi, D. Madadi.  Realization of Double-Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer. Phys. Status Solidi., 219 (21) (Nov. 2022) 2200214. Available: https://doi.org/10.1002/pssa.202200214

[32]M. Bavir, A. Abbasi, Ali. A. Orouji.  Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet. IEEE J. Electron Devices Soc., 10 (Apr. 2022) 334-340. Available: https://doi.org/10.1109/JEDS.2022.3166708

[33]ATLAS Device Simulation Software, Silvaco, Santa Clara, CA, USA, 2019. Available: https://silvaco.com/

[34]J.-P. Colinge, J. C. Alderman, W. Xiong, and C. R. Cleavelin, Quantum–mechanical effects in trigate SOI MOSFETs. IEEE Trans. Electron Devices, 53 (5) (May. 2006) 1131–1136. Available: https://doi.org/10.1109/TED.2006.871872