An Ultra-Low-Power and Full-Swing Full Adder Cell

Subject Areas : Majlesi Journal of Telecommunication Devices

Soorena  Zohoori ¹ ()
Mehdi  Dolatshahi ² ()

Received: 2018-09-17 Accepted : 2018-09-18 Published : 2018-09-01

Keywords: GDI, ultra-low-power, Full adder,

Abstract :

In this paper, a one-bit ultra-low-power full adder cell using GDI structure is proposed. Main objective of this design is not only providing low power consumption, but also providing full swing outputs. In this paper, combination of different logics and stacking technique are used to provide an ultra-low power cell. Also, by using stacked inverters after each function, full swing characteristic for the cell is obtained. These characteristics are obtained in cost of more occupied chip area and higher delay. In order to verify the performance of the proposed cell, simulations are done in HSPICE using 90nm CMOS technology library. Beside Noise immunity, power consumption is also analyzed under different load conditions, different supply voltages and different temperatures. Although delay of the circuit is increased, results show a tremendous reduction in power consumption and an improved power-delay-product for the proposed full adder cell.

References:

[1] V. Foroutan, M. Taheri, Keivan Navi, A. Azizi Mazreah, “Design of two Low-power full adder cells Using GDI structure and Hybrid CMOS Logic Style”, INTEGRATIN: the VLSI journal (Elsevier), 47, pp. 48-61, 2014.

[2] R. Gu, M. Elmasry, “ Power dissipation analysis and optimization of deep submicron CMOS digital Circuits”, IEEE Journal of Solid-State Circuits, 31 (5), pp. 707-713, 1996.

[3] C.H. Chang, G.M. Zhang, “A review of 0.18um full-adder performance for tree structure arithmetic circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13 (6), 2005.

[4] Y. Jiang, A. Sheraidah, Y. Wang, E. sha, J. Chung, “ A novel multiplexer based low power full adder”, IEEE Transactions on circuits and systems II, 51 (7), 2004.

[5] M. Vai, “VLSI Design”, CRC Press, Boca Raton, FL, 2001.

[6] V. Dessard, “ SOI Specific Analog Techniques for low noise, high performance or Ultra low power Circuits”, Ph.D. Thesis, UCL, Louvain, Belgium, 2001.

[7] D. Hassoune, I. Flandre, Connor, J. legat, “ULPFA: a new efficient design of a power aware full adder”, IEEE Transaction on Circuits and Systems, 57 (8), 2010.

[8] D. Levacq, C. Liber, V. Dessard, D. Flandre, “Composite ULP diode fabrication modeling and applications in multi-FD SOI CMOS technology”, Solid State Electronics, 48 (6), pp. 1017-1025, 2010.

[9] M. Alioto, “Ultra low power VLSI Circuit design demystified and explained”, IEEE Transactions on Circuits and Systems on Circuits and Systems, 59 (1), pp. 3-29, 2012.

[10] D. Bol, “Robust and energy efficient ultra low voltage circuit design under timing constraints in 65/45nm CMOS”, Journal of Low Power Electronics and Applications, 1 (1), pp. 1-19, 2011.

[11] G. Chen, M. Fojtik, D. Kim, and etc., “Millimeter scale nearly perpetual sensor system with stacked battery and solar cells”, In Proceedings of IEEE International Solid State Circuits Conference digest of technical papers (ISSCC), 2010, pp. 288-289.

[12] I. Vaisband, E. G. Friedman, r. Ginosar, A. Kolodny, “Low-power Clock network design”, Journal of Low Power Electronics and Applications, pp. 219-246, 2011.

[13] A. Morgenshtein, A. Fish, I. Wagner, “Gate Diffusion input (GDI)- a power efficient method for digital combinatorial circuits”, IEEE Transactions on VLSI systems, 10 (5), 2002.

[14] M. Kumar, M. A. Hussain, L.L.K. Singh, “Design of a low power high speed ALU in 45nm Using GDI technique and its performance comparison communications in computer and information science’’, 142 (part 3), pp. 458-463, 2011.

[15] K. Chaddha, R. Chandel, “Design and analysis of a modified low power CMOS full adder using gate-diffusion input technique”, journal of low power electronics, 6 (4), pp. 482-490, 2010.

[16] O.P. Hari, A. Mai, “Low power and area efficient implantation of N-phase non overlapping clock generator using GDI technique”, in Proceedings of IEEE International Conference on Electronics Computer Technology (ICECT), 2011.

[17] P.M. Lee, C. Hsu, Y. Hung, “Novel 10-T full adders realized by GDI structure”, in: proceeding of the IEEE International Symposium on integrated Circuits, 2007.

[18] F. Moradi, D.T. Wisland, D.T.H Mahmoodi, H. Aunet, T.V. Cao, A. Peiravi, “Ultra Low power full adder topologies”, in: proceedings of ISCAS’04, Taipei, Taiwan, 2009.

[19] A. Morgenshtein, A. Fish, I.A. Wagner, “An efficient implementation of D-Flip flop using the GDI technique”, in: proceedings of ISCAS’04 Conference, Canada, pp. 673-676, 2004.

[20] R. Uma, P. Dhavachelvan, “Modified gate diffusion input technique”, a new technique for enhancing performance in full adder circuits, proceeding of ICCCS6, pp. 74-81, 2012.

[21] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, A. Fish, “Full-swing Gate Diffusion Input Logic-case-study of low Power CLA adder design”, INTEGRATION: the VLSI Journal (Elsevier), 47, pp. 62-70, 2014.

[22] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, A. Fish, “Full-Swing Gate Diffusion Logic-Case-Study of low-Power CLA adder design”, INTEGRATION the VLSI Journal (Elsevier), 47, pp. 62-70, 2014.

[23] A. Morgenstein, I. Shwartz, A. Fish, “Gate diffusion input (GDI)-a power efficient method for digital combinatorial circuits”, IEEE Transactions on VLSI Systems, 10 (5), 2002.

[24] M.G. Priya, K. Baskaran, D. Krishnaveni, “ Leakage power Reduction technique in deep Submicron Technologies for VLSI Applications”, International Conference on Communication technology and System Design, pp. 1163-1170, 2012.