تفریق¬کننده¬های تک¬بیتی تقریبی مبتنی ¬بر تکنیک GDI با راندمان انرژی بالا و مساحت پایین برای پیاده¬سازی تقسیم¬کننده¬ها
محورهای موضوعی : مهندسی الکترونیک
فاطمه پولادی
1
,
فرشاد پسران
2
,
نبي اله شیری
3
1 - گروه مهندسی برق، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران
2 - دانشگاه آزاد اسلامی، واحد شیراز
3 - استاد دانشکاه آزاد شیراز-صدرا
کلید واژه: تفریق¬کننده, تقسیم¬کننده, محاسبات ¬تقریبی, نانو¬لوله¬کربنی,
چکیده مقاله :
در مدارهای دیجیتال با ترانزیستورهای زیاد، انرژی مصرفی بالا همچنان چالش اساسی می¬باشد. تکنیک¬های نوظهور مانند محاسبات تقریبی تا حدودی به حل این چالش کمک کرده¬اند. بر این اساس، سه تفریق¬کننده جدید تک¬بیتی بر مبنای محاسبات¬ تقریبی و تکنیک دروازه ورودی انتشار معرفی می¬شوند. مدارهای پیشنهادی 1 تا 3 ضمن جدول درستی متفاوت با دیگر مدارها، به¬ترتیب 10، 8، و 6 ترانزیستور دارند که باعث کاهش قابل¬توجه توان¬مصرفی می¬شود. نتایج شبیه¬سازی¬ براساس تکنولوژی ترانزیستور اثر میدانی نانولوله کربنی (CNTFET) با طول کانال 32 نانومتری، برتری این مدارها را تایید می¬کند. مدار پیشنهادی 3 بدون استفاده از اینورتر، دارای بهترین عملکرد از نظر مداری می¬باشد. هر چند به¬دلیل وجود 4 خطا در این مدار، نرخ خطای آن در مقایسه با دیگر مدارها بیشتر می¬باشد. بررسی اثرات تغییرات در منبع ولتاژ، fan-out و تغییرات فرایند-ولتاژ-دما گویای برتری مدار پیشنهادی 3 از نظر انرژی¬ تلفاتی می¬باشد. هم¬چنین، با تعبیه مدارهای پیشنهادی در ساختار تقسیم¬کننده 8¬ بیتی، برتری مدار پیشنهادی 3 از¬ نظر معیارهای شایستگی مختلف به مقدار حداقل 50% قابل مشاهده است.
In digital circuits that have a high number of transistors, energy dissipation is still a challenge. New techniques like approximate computing are somehow helpful for challenge solving. Therefore, three new single-bit subtractors are presented based on the approximate computing and gate diffusion input (GDI) technique. Compared to the literature, proposed circuits 1-3 with different truth tables have 10, 8, and 6 transistors, respectively, which causes a significant reduction in power consumption. The simulation results based on the carbon nanotube field effect transistor (CNTFET) technology with a channel length of 32 nm confirmed the superiority of the circuits. The proposed circuit 3 with no inverter has the best circuitry performance. However, due to the presence of 4 errors in this circuit, its error rate is higher compared to other circuits. Examining the effects of changes in the voltage source, the fan-outs, and the process-voltage-temperature (PVT) variations showed a superior energy performance of the proposed circuit 3. Also, by embedding the proposed circuits in the 8-bit divider structure, the superiority of the proposed circuit 3 in terms of various figures of merits was observable by at least 50%.
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