طراحی یک مقایسه کننده کم توان سرعت بالا با سطح اشغالی کم در فناوری فین فت ۶۵ نانومتری
محورهای موضوعی : مهندسی الکترونیک
نوید سبزواری
1
,
محمدرضا یوسفی
2
,
سیدمحمدعلی زنجانی
3
1 - گروه مهندسی برق، دانشگاه آزاد اسلامی واحد نجف آباد، نجف آباد، ایران
2 - مرکز تحقیقات ریز شبکه های هوشمند، دانشگاه آزاد اسلامی واحد نجف آباد، نجف آباد، ایران
3 - مرکز تحقیقات ریزشبکه های هوشمند، دانشگاه آزاد اسلامی واحد نجف آباد، نجف آباد، ایران
کلید واژه: سرعت بالا, سطح کم اشغالی, کم توان, ترانزیستور اثر میدان باله‌ای, مقایسه‌کننده,
چکیده مقاله :
در این مقاله، یک مدار مقایسه کننده جدید کم توان و پرسرعت به کمک ترانزیستور اثر میدان باله ای (Finfet) در فناوری 65 نانومتری طراحی شده است. علاوه بر این، با استفاده صحیح از قابلیت های فناوری Finfet، تعداد ترانزیستورها کاهش یافته و درنتیجه، سطح کمتری اشغال می شود. جایگزینی ترانزیستورهای MOSFET با Finfet باعث کاهش تأخیر و مصرف توان مدار شده، عملکرد کلی مدار بهبود می یابد. اولین نوآوری در طرح پیشنهادی این است که برای کاهش اندازه و مصرف توان، دو ترانزیستور حذف شده اند و گیتهای پشتی دو ترانزیستور به صورت متقاطع قرار گرفته اند. نوآوری دوم، اتصال گیتهای پشتی به نقاط مناسبی از مدار است که سرعت مقایسه را افزایش می دهد. در این مطالعه، تغذیه 0.8 ولت به مدار اعمال می شود تا نشان دهد که مدار پیشنهادی با Finfet باعث کاهش تأخیر به 272 پیکوثانیه و مصرف توان به 6.7میکرووات می شود.
In the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and subsequently, a smaller area is occupied. Replacing MOSFET transistors with FinFETs reduces the delay and power consumption of the circuit, so the overall performance is improved. The first innovation of the proposed design is that to reduce the size and power consumption, two transistors were removed and the back gates of two transistors were cross-coupled. The second innovation is the connection of back gates to other suitable points of the circuit that increase the speed of comparison. In this study, a supply voltage of 0.8 V is applied to the circuit to show that the proposed modifications with FinFET reduce the delay to 272 ps and power consumption to 6.7 µW.
[1] A. Khorami and M. Sharifkhani, "A low-power high-speed comparator for precise applications", IEEE Trans. on Very Large-Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2038-2049, 2018 ,doi: 10.1109/TVLSI.2018.2833037.
[2] A. Baghi Rahin, V. Baghi Rahin, “A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders”, Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 13-22, 2019 ,dor: 20.1001.1.23223871.1398.10.37.2.6.
[3] I. Chakraborty, A. Agrawal, K. Roy, "Design of a low-voltage analog-to-digital converter using voltage-controlled stochastic switching of low barrier nanomagnets", IEEE Magnetics Letters, vol. 9, pp. 1-5, May 2018 ,doi: 10.1109/LMAG.2018.2839097.
[4] O. Aiello, P. Crovetti, M. Alioto, "Fully synthesizable low-area analogue-to-digital converters with minimal design effort based on the dyadic digital pulse modulation", IEEE Access, vol. 8, pp. 70890-70899, April 2020 ,doi: 10.1109/ACCESS.2020.2986949.
[5] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan, J.J. Liou, "A low-power high-speed dynamic comparator with a transconductance-enhanced latching stage", IEEE Access, vol. 7, pp. 93396-93403, 2019 ,doi: 10.1109/ACCESS.2019.2927514.
[6] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, “Inverter‐based, low‐power and low‐voltage, new mixed‐mode Gm‐C filter in subthreshold CNTFET technology”, IET Circuits, Devices & Systems, vol. 12, no. 6, pp. 681-688, 2018 ,doi: 10.1049/iet-cds.2018.5158.
[7] Y. Cai et al., "Endurance characteristics of negative capacitance FinFETs with negligible hysteresis", IEEE Electron Device Letters, vol. 42, no. 2, pp. 260-263, Feb. 2021 ,doi: 10.1109/LED.2020.3048349.
[8] V. Varshney, R.K. Nagaria, “Design and analysis of ultra-high-speed low-power double tail dynamic comparator using charge sharing scheme”, International Journal of Electronics and Communications, vol. 116, Article paper: 153068, 2020 ,doi: 10.1016/j.aeue.2020.153068.
[9] A. Baghi Rahin, V. Baghi Rahin, “Ultra low voltage and low power 4-2 compressor using FinFET transistors”, Journal of Intelligent Procedures in Electrical Technology, vol. 9, no. 33, pp. 25-36, June 2018 ,dor: 20.1001.1.23223871.1397.9.33.3.2.
[10] Y.J. Chang, K.L. Tsai, Y.C. Cheng, M.R. Lu, “Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment”, Computers and Electrical Engineering, vol. 81, no. 106528, Jan, 2020,doi:10.1016/j.compeleceng.2019.106528.
[11] E. Yu, K. Heo, S. Cho, "Characterization and optimization of inverted-T FinFET under nanoscale dimensions", IEEE Trans. on Electron Devices, vol. 65, no. 8, pp. 3521-3527, Aug. 2018 ,doi: 10.1109/TED.2018.2846478.
[12] S. Garg, T.K. Gupta, “A new technique for designing low-power high-speed domino logic circuits in FinFET technology”, Journal of Circuits, Systems and Computers, vol. 28, no. 10, no. 1950165, 2019 ,doi: 10.1142/S0218126619501652.
[13] S. Babayan-Mashhadi, R. Lotfi, “Analysis and design of a low-voltage low-power double tail comparator”, IEEE. Trans. on Very Large-Scale Integration (VLSI) system, vol. 22, no. 2, pp. 343-352, Feb. 2014, doi: 10.1109/TVLSI.2013.2241799.
[14] G. Leung, S. Wang, A. Pan, P. Gupta and C. O. Chui, "An evaluation framework for nanotransfer printing-based feature-level heterogeneous integration in VLSI circuits", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1858-1870, May 2016 ,doi: 10.1109/TVLSI.2015.2477282.
[15] R. Kuo, F. Chang, Y. King, C. Lin, "Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process", IEEE Trans. on Electron Devices, vol. 66, no. 4, pp. 1729-1733, 2019.B. Swahn, S. Hassoun, “Gate sizing: FinFETs vs 32nm Bulk MOSFETs”, Proceedings of the IEEE/ACM, pp. 528–531, 2006, doi: 10.1109/TED.2019.2900282.
[16] S. Daneshgar et al., "High-power generation for mm-wave 5G power amplifiers in deep sub micrometer planar and FinFET bulk CMOS", IEEE Trans. on Microwave Theory and Techniques, vol. 68, no. 6, pp. 2041-2056, 2020, doi: 10.1109/TMTT.2020.2990638.
[17] N. Agrawal, H. Liu, R. Arghavani, V. Narayanan, S. Datta, "Impact of variation in nano scale silicon and non-silicon FinFETs and tunnel FETs on device and SRAM performance", IEEE Trans. on Electron Devices, vol. 62, no. 6, pp. 1691-1697, 2015, doi: 10.1109/TED.2015.2406333.
[18] X. Zhang, et. al. "Analysis of 7/8-nm bulk-Si FinFET technologies for 6T-SRAM scaling", IEEE Trans. on Electron devices, vol. 63, no. 4, pp. 1502-1507, 2016, doi: 10.1109/TED.2016.2523885.
[19] A.G. Akkala, R. Venkatesan, A. Raghunathan, K. Roy, "Asymmetric underlapped sub-10-nm n-FinFETs for high-speed and low-leakage 6T SRAMs", IEEE Trans. on Electron Devices, vol.63, no. 3, pp. 1034-1040, 2016, doi: 10.1109/TED.2015.2512227.
[20] G. Pasandi, S.M. Fakhraie, "An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs", IEEE Trans. on Electron Devices, vol. 61, no. 7, pp. 2357- 2363, 2014, doi: 10.1109/TED.2014.2321295.
[21] M. Monica, P. Chandramohan, "Characterization of 8T SRAM cells using 16 nm FinFET technology", Proceeding of the IEEE/ICSC, pp. 403-406, Noida, India, Dec. 2016, doi:10.1109/ICSPCom.2016.7980614.
[22] Y. Yang, J. Park, S.C. Song, J. Wang, G. Yeap, S. Jung, "Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology", IEEE Trans. on Very Large-Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2748-2752, Nov. 2015, doi: 10.1109/TVLSI.2014.2367234.
[23] N. Sharma, "Ultra low power dissipation in 9T SRAM design by using FinFET technology", Proceeding of the IEEE/ICTBIG, pp. 1-5, Indore, India, Nov. 2016, doi: 10.1109/ICTBIG.2016.7892657.
[24] A. Guler, N.K. Jha, "Three-dimensional monolithic FinFET-based 8T SRAM cell design for enhanced read time and low leakage", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 4, pp. 899-912, April 2019, doi: 10.1109/TVLSI.2018.2883525.
[25] M.U. Mohammed, M.H. Chowdhury, "Reliability and energy efficiency of the tunneling transistor-based 6T SRAM cell in sub-10 nm domain", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 65, no. 12, pp. 1829-1833, Dec. 2018, doi: 10.1109/TCSII.2018.2874897.
[26] M. Aghaei Jeshvaghani, M. Dolatshahi, “Design of a low-power universal Gm-C filter in sub-threshold region”, Journal of Intelligent Procedures in Electrical Technology, vol. 4, no. 15, pp. 3-10, 2013, dor: 20.1001.1.23223871.1392.4.15.1.9.
[27] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, “A new low-power, universal, multi-mode Gm-C filter in CNTFET technology”, Microelectronics Journal, vol. 90, pp. 342-352, 2019, doi: 10.1016/j.mejo.2019.01.003.
[28] S. Chaudhuri, N.K. Jha, “3D vs. 2D analysis of FinFET logic gates under process variations”, Proceedings of the IEEE/ICCD, pp. 435–436, 2011, doi: 10.1109/ICCD.2011.6081437.
[29] M. Xu et al., "Improved short channel effect control in bulk FinFETs with vertical implantation to form self-aligned halo and punch-through stop pocket", IEEE Electron Device Letters, vol. 36, no. 7, pp. 648-650, July 2015, doi: 10.1109/LED.2015.2434825.
[30] B. Raj, A.K. Saxena, S. Dasgupta, "Nanoscale FinFET based SRAM cell design: Analysis of performance metric, process variation, underlapped FinFET, and temperature effect", IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38-50, 2011, doi: 10.1109/MCAS.2011.942068.
[31] R. Chang, C. Lin and M. Ker, "Design of fin-diode-triggered rotated silicon-controlled rectifier for high- speed digital application in 16-nm FinFET process", IEEE Trans. on Electron Devices, vol. 67, no. 7, pp. 2725-2731, July 2020, doi: 10.1109/TED.2020.2995145.
[32] S.M.A. Zanjani, N. Chamanpira, M. Dolatshahi, "Design and simulation of a new sample and hold circuit with a resolution of 12-bit and a sampling rate of 1 GS/s using a dual sampling technique", Journal of Intelligent Procedures in Electrical Technology, vol. 9, no. 34, pp. 3-10, 2018, dor: 20.1001.1.23223871.1397.9.34.1.2.
_||_[1] A. Khorami and M. Sharifkhani, "A low-power high-speed comparator for precise applications", IEEE Trans. on Very Large-Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2038-2049, 2018 ,doi: 10.1109/TVLSI.2018.2833037.
[2] A. Baghi Rahin, V. Baghi Rahin, “A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders”, Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 13-22, 2019 ,dor: 20.1001.1.23223871.1398.10.37.2.6.
[3] I. Chakraborty, A. Agrawal, K. Roy, "Design of a low-voltage analog-to-digital converter using voltage-controlled stochastic switching of low barrier nanomagnets", IEEE Magnetics Letters, vol. 9, pp. 1-5, May 2018 ,doi: 10.1109/LMAG.2018.2839097.
[4] O. Aiello, P. Crovetti, M. Alioto, "Fully synthesizable low-area analogue-to-digital converters with minimal design effort based on the dyadic digital pulse modulation", IEEE Access, vol. 8, pp. 70890-70899, April 2020 ,doi: 10.1109/ACCESS.2020.2986949.
[5] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan, J.J. Liou, "A low-power high-speed dynamic comparator with a transconductance-enhanced latching stage", IEEE Access, vol. 7, pp. 93396-93403, 2019 ,doi: 10.1109/ACCESS.2019.2927514.
[6] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, “Inverter‐based, low‐power and low‐voltage, new mixed‐mode Gm‐C filter in subthreshold CNTFET technology”, IET Circuits, Devices & Systems, vol. 12, no. 6, pp. 681-688, 2018 ,doi: 10.1049/iet-cds.2018.5158.
[7] Y. Cai et al., "Endurance characteristics of negative capacitance FinFETs with negligible hysteresis", IEEE Electron Device Letters, vol. 42, no. 2, pp. 260-263, Feb. 2021 ,doi: 10.1109/LED.2020.3048349.
[8] V. Varshney, R.K. Nagaria, “Design and analysis of ultra-high-speed low-power double tail dynamic comparator using charge sharing scheme”, International Journal of Electronics and Communications, vol. 116, Article paper: 153068, 2020 ,doi: 10.1016/j.aeue.2020.153068.
[9] A. Baghi Rahin, V. Baghi Rahin, “Ultra low voltage and low power 4-2 compressor using FinFET transistors”, Journal of Intelligent Procedures in Electrical Technology, vol. 9, no. 33, pp. 25-36, June 2018 ,dor: 20.1001.1.23223871.1397.9.33.3.2.
[10] Y.J. Chang, K.L. Tsai, Y.C. Cheng, M.R. Lu, “Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment”, Computers and Electrical Engineering, vol. 81, no. 106528, Jan, 2020,doi:10.1016/j.compeleceng.2019.106528.
[11] E. Yu, K. Heo, S. Cho, "Characterization and optimization of inverted-T FinFET under nanoscale dimensions", IEEE Trans. on Electron Devices, vol. 65, no. 8, pp. 3521-3527, Aug. 2018 ,doi: 10.1109/TED.2018.2846478.
[12] S. Garg, T.K. Gupta, “A new technique for designing low-power high-speed domino logic circuits in FinFET technology”, Journal of Circuits, Systems and Computers, vol. 28, no. 10, no. 1950165, 2019 ,doi: 10.1142/S0218126619501652.
[13] S. Babayan-Mashhadi, R. Lotfi, “Analysis and design of a low-voltage low-power double tail comparator”, IEEE. Trans. on Very Large-Scale Integration (VLSI) system, vol. 22, no. 2, pp. 343-352, Feb. 2014, doi: 10.1109/TVLSI.2013.2241799.
[14] G. Leung, S. Wang, A. Pan, P. Gupta and C. O. Chui, "An evaluation framework for nanotransfer printing-based feature-level heterogeneous integration in VLSI circuits", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1858-1870, May 2016 ,doi: 10.1109/TVLSI.2015.2477282.
[15] R. Kuo, F. Chang, Y. King, C. Lin, "Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process", IEEE Trans. on Electron Devices, vol. 66, no. 4, pp. 1729-1733, 2019.B. Swahn, S. Hassoun, “Gate sizing: FinFETs vs 32nm Bulk MOSFETs”, Proceedings of the IEEE/ACM, pp. 528–531, 2006, doi: 10.1109/TED.2019.2900282.
[16] S. Daneshgar et al., "High-power generation for mm-wave 5G power amplifiers in deep sub micrometer planar and FinFET bulk CMOS", IEEE Trans. on Microwave Theory and Techniques, vol. 68, no. 6, pp. 2041-2056, 2020, doi: 10.1109/TMTT.2020.2990638.
[17] N. Agrawal, H. Liu, R. Arghavani, V. Narayanan, S. Datta, "Impact of variation in nano scale silicon and non-silicon FinFETs and tunnel FETs on device and SRAM performance", IEEE Trans. on Electron Devices, vol. 62, no. 6, pp. 1691-1697, 2015, doi: 10.1109/TED.2015.2406333.
[18] X. Zhang, et. al. "Analysis of 7/8-nm bulk-Si FinFET technologies for 6T-SRAM scaling", IEEE Trans. on Electron devices, vol. 63, no. 4, pp. 1502-1507, 2016, doi: 10.1109/TED.2016.2523885.
[19] A.G. Akkala, R. Venkatesan, A. Raghunathan, K. Roy, "Asymmetric underlapped sub-10-nm n-FinFETs for high-speed and low-leakage 6T SRAMs", IEEE Trans. on Electron Devices, vol.63, no. 3, pp. 1034-1040, 2016, doi: 10.1109/TED.2015.2512227.
[20] G. Pasandi, S.M. Fakhraie, "An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs", IEEE Trans. on Electron Devices, vol. 61, no. 7, pp. 2357- 2363, 2014, doi: 10.1109/TED.2014.2321295.
[21] M. Monica, P. Chandramohan, "Characterization of 8T SRAM cells using 16 nm FinFET technology", Proceeding of the IEEE/ICSC, pp. 403-406, Noida, India, Dec. 2016, doi:10.1109/ICSPCom.2016.7980614.
[22] Y. Yang, J. Park, S.C. Song, J. Wang, G. Yeap, S. Jung, "Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology", IEEE Trans. on Very Large-Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2748-2752, Nov. 2015, doi: 10.1109/TVLSI.2014.2367234.
[23] N. Sharma, "Ultra low power dissipation in 9T SRAM design by using FinFET technology", Proceeding of the IEEE/ICTBIG, pp. 1-5, Indore, India, Nov. 2016, doi: 10.1109/ICTBIG.2016.7892657.
[24] A. Guler, N.K. Jha, "Three-dimensional monolithic FinFET-based 8T SRAM cell design for enhanced read time and low leakage", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 4, pp. 899-912, April 2019, doi: 10.1109/TVLSI.2018.2883525.
[25] M.U. Mohammed, M.H. Chowdhury, "Reliability and energy efficiency of the tunneling transistor-based 6T SRAM cell in sub-10 nm domain", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 65, no. 12, pp. 1829-1833, Dec. 2018, doi: 10.1109/TCSII.2018.2874897.
[26] M. Aghaei Jeshvaghani, M. Dolatshahi, “Design of a low-power universal Gm-C filter in sub-threshold region”, Journal of Intelligent Procedures in Electrical Technology, vol. 4, no. 15, pp. 3-10, 2013, dor: 20.1001.1.23223871.1392.4.15.1.9.
[27] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, “A new low-power, universal, multi-mode Gm-C filter in CNTFET technology”, Microelectronics Journal, vol. 90, pp. 342-352, 2019, doi: 10.1016/j.mejo.2019.01.003.
[28] S. Chaudhuri, N.K. Jha, “3D vs. 2D analysis of FinFET logic gates under process variations”, Proceedings of the IEEE/ICCD, pp. 435–436, 2011, doi: 10.1109/ICCD.2011.6081437.
[29] M. Xu et al., "Improved short channel effect control in bulk FinFETs with vertical implantation to form self-aligned halo and punch-through stop pocket", IEEE Electron Device Letters, vol. 36, no. 7, pp. 648-650, July 2015, doi: 10.1109/LED.2015.2434825.
[30] B. Raj, A.K. Saxena, S. Dasgupta, "Nanoscale FinFET based SRAM cell design: Analysis of performance metric, process variation, underlapped FinFET, and temperature effect", IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38-50, 2011, doi: 10.1109/MCAS.2011.942068.
[31] R. Chang, C. Lin and M. Ker, "Design of fin-diode-triggered rotated silicon-controlled rectifier for high- speed digital application in 16-nm FinFET process", IEEE Trans. on Electron Devices, vol. 67, no. 7, pp. 2725-2731, July 2020, doi: 10.1109/TED.2020.2995145.
[32] S.M.A. Zanjani, N. Chamanpira, M. Dolatshahi, "Design and simulation of a new sample and hold circuit with a resolution of 12-bit and a sampling rate of 1 GS/s using a dual sampling technique", Journal of Intelligent Procedures in Electrical Technology, vol. 9, no. 34, pp. 3-10, 2018, dor: 20.1001.1.23223871.1397.9.34.1.2.