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دسترسی آزاد مقاله
1 - طراحی یک مقایسه کننده کم توان سرعت بالا با سطح اشغالی کم در فناوری فین فت ۶۵ نانومتری
نوید سبزواری محمدرضا یوسفی سیدمحمدعلی زنجانیدر این مقاله، یک مدار مقایسه کننده جدید کم توان و پرسرعت به کمک ترانزیستور اثر میدان باله ای (Finfet) در فناوری 65 نانومتری طراحی شده است. علاوه بر این، با استفاده صحیح از قابلیت های فناوری Finfet، تعداد ترانزیستورها کاهش یافته و درنتیجه، سطح کمتری اشغال می شود. جا چکیده کاملدر این مقاله، یک مدار مقایسه کننده جدید کم توان و پرسرعت به کمک ترانزیستور اثر میدان باله ای (Finfet) در فناوری 65 نانومتری طراحی شده است. علاوه بر این، با استفاده صحیح از قابلیت های فناوری Finfet، تعداد ترانزیستورها کاهش یافته و درنتیجه، سطح کمتری اشغال می شود. جایگزینی ترانزیستورهای MOSFET با Finfet باعث کاهش تأخیر و مصرف توان مدار شده، عملکرد کلی مدار بهبود می یابد. اولین نوآوری در طرح پیشنهادی این است که برای کاهش اندازه و مصرف توان، دو ترانزیستور حذف شده اند و گیتهای پشتی دو ترانزیستور به صورت متقاطع قرار گرفته اند. نوآوری دوم، اتصال گیتهای پشتی به نقاط مناسبی از مدار است که سرعت مقایسه را افزایش می دهد. در این مطالعه، تغذیه 0.8 ولت به مدار اعمال می شود تا نشان دهد که مدار پیشنهادی با Finfet باعث کاهش تأخیر به 272 پیکوثانیه و مصرف توان به 6.7میکرووات می شود. پرونده مقاله -
دسترسی آزاد مقاله
2 - Droplet Counter Current Chromatography (DCCC) in herbal analysis
Lutfun Nahar Satyajit D. SarkerAbout half a century ago, the separation science was blessed with the introduction of a new liquid-liquid separation technique called droplet counter current chromatography (DCCC) that combined principles of counter current distribution and counter current chromatograph چکیده کاملAbout half a century ago, the separation science was blessed with the introduction of a new liquid-liquid separation technique called droplet counter current chromatography (DCCC) that combined principles of counter current distribution and counter current chromatography, and employed a liquid stationary phase held in a cluster of vertical glass columns connected in series. In fact, DCCC is based on the partitioning of solutes between a constant stream of droplets of mobile phase and a column of surrounding stationary phase. پرونده مقاله -
دسترسی آزاد مقاله
3 - Analysis and Design of a High Performance Radix-4 Booth Scheme in CMOS Technology
Ali RahnamaeiIn this paper, a novel high performance structure has been demonstrated which can be widely used for circuit-level realization of radix-4 Booth scheme. The notable privilege of proposed scheme is its higher speed for generation of Partial Products (PPs) compared to the چکیده کاملIn this paper, a novel high performance structure has been demonstrated which can be widely used for circuit-level realization of radix-4 Booth scheme. The notable privilege of proposed scheme is its higher speed for generation of Partial Products (PPs) compared to the previous designs. The objective has been achieved by means of the modified truth table of Booth algorithm. Moreover, Pass-Transistor Logic (PTL) has been employed to reduce the middle stage capacitances which has considerably enhanced the operating frequency of the designed architecture. The thorough analysis over previously reported works has also been provided to help the authors for optimized implementation of the Booth circuitry. Simulation results for TSMC 0.18µm CMOS technology and 1.8V power supply using HSPICE indicate the correct operation of the proposed scheme. In addition, the best-reported works have been redesigned and simulated on the same conditions to provide a fair comparative environment with our designed scheme. The results demonstrate the superiority of our circuit over the selected structures. پرونده مقاله -
دسترسی آزاد مقاله
4 - High-Speed Ternary Half adder based on GNRFET
Mahdieh Nayeri Peiman Keshavarzian Maryam NayeriSuperior electronic properties of graphene make it a substitute candidate for beyond-CMOS nanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, and quantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have sem چکیده کاملSuperior electronic properties of graphene make it a substitute candidate for beyond-CMOS nanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, and quantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior, are used to design the digital circuits. This paper presents a new design of ternary half adder based on graphene nanoribbon FETs (GNRFETs). Because of reducing chip area and integrated circuit (IC) interconnects, ternary value logic is a good alternative to binary logic. Extensive simulations have been performed in Hspice with 15-nm GNRFET technology to investigate the power consumption and delay. Results show that the proposed design is very high-speed in comparison with carbon nanotube FETs (CNTFETs). The proposed ternary half adder based on GNRFET at 0.9V exhibiting a low power-delay-product (PDP) of ~10-20 J, which is a high improvement in comparison with the ternary circuits based on CNTFET, lately proposed in the literature. This proposed ternary half adder can be advantageous in complex arithmetic circuits. پرونده مقاله -
دسترسی آزاد مقاله
5 - High-Speed Ternary Half adder based on GNRFET
Mahdieh Nayeri Peiman Keshavarzian Maryam NayeriSuperior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semic چکیده کاملSuperior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,are used to design the digital circuits. This paper presents a new design of ternary half adder basedon graphene nanoribbon FETs (GNRFETs). Due to reducing chip the area and integrated circuit (IC)interconnects, ternary value logic is a good alternative to binary logic. Extensive simulations have beenperformed in Hspice with 15-nm GNRFET technology to investigate the power consumption and delay.Results show that the proposed design is very high-speed in comparison with carbon nanotube FETs(CNTFETs). The proposed ternary half adder based on GNRFET at 0.9V exhibiting a low power-delayproduct(PDP) of ~10-20 J, which is a high improvement in comparison with the ternary circuits basedon CNTFET, lately proposed in the literature. This proposed ternary half adder can be advantageous incomplex arithmetic circuits. پرونده مقاله -
دسترسی آزاد مقاله
6 - Low Complexity Converter for the Moduli Set {2^n+1,2^n-1,2^n} in Two-Part Residue Number System
Shiva TaghipourResidue Number System is a kind of numerical systems that uses the remainder of division in several different moduli. Conversion of a number to smaller ones and carrying out parallel calculations on these numbers will increase the speed of the arithmetic operations in t چکیده کاملResidue Number System is a kind of numerical systems that uses the remainder of division in several different moduli. Conversion of a number to smaller ones and carrying out parallel calculations on these numbers will increase the speed of the arithmetic operations in this system. However, the main factor that affects performance of system is hardware complexity of reverse converter. Reverse converters convert the resulted remainders to the conventional number system. In this paper an area efficient reverse converter is proposed for moduli set {2^n+1,2^n-1,2^n} based on two-part RNS and mixed radix conversion algorithm. Selecting appropriate order of modulus and using well-known lemmas, leads to reduce the complexity of the proposed converter comparing to previous designs. To have an accurate comparison, both unit gate model and simulation in Xilinx 13.1 FPGA are used in this paper. The results of comparison indicate that the novel proposed reverse converter has improved the time complexity and area, while having almost same delay. پرونده مقاله -
دسترسی آزاد مقاله
7 - Very High Throughput Implementation of Advanced Encryption Standard (AES) Algorithm on FPGA
Mahdi Rahmanpour Amir Amirabadi ZavareAn Advanced Encryption Standard (AES) algorithm is one of the most popular and most commonly used encryption algorithms. This algorithm can be implemented on microcontroller chips and FPGAs with various specifications. Also, the goals of implementing this algorithm are چکیده کاملAn Advanced Encryption Standard (AES) algorithm is one of the most popular and most commonly used encryption algorithms. This algorithm can be implemented on microcontroller chips and FPGAs with various specifications. Also, the goals of implementing this algorithm are varied according to the application and requirements. In this paper, a project has been given that output very high data transfer rate equal 192 Gbps on the FPGA of the Virtex-7 (XC7VX330T-3FFG1157) from Xilinx. The extracted results of the implementation of the algorithm in the ISE 14.7 software show the maximum achievable clock frequency 500 MHz, with the parallel implementation of than three AES algorithms cores on a chip, higher speeds are also available. پرونده مقاله
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