طراحی و شبیه سازی سلول حافظه دسترسی تصادفی ایستا با توان مصرفی پایین مبتنی بر ترانزیستور فین‌فت

محورهای موضوعی : مهندسی برق الکترونیک

فاطمه ذوالفقاری سیچانی ¹ , محمد روح اله یزدانی ² , عاطفه سلیمی ³ , مریم منعمیان ⁴

1 - دانشکده مهندسی برق، واحد اصفهان (خوراسگان)، دانشگاه آزاد اسلامی، خوراسگان، اصفهان، ایران
2 - دانشکده مهندسی برق، واحد اصفهان (خوراسگان)، دانشگاه آزاد اسلامی، خوراسگان، اصفهان، ایران
3 - دانشکده مهندسی برق، واحد اصفهان (خوراسگان)، دانشگاه آزاد اسلامی، خوراسگان، اصفهان، ایران
4 - مرکز تحقیقات پردازش تصویر و سیگنال پزشکی، دانشگاه علوم پزشکی اصفهان، اصفهان، ایران

تاریخ دریافت : 1401/11/25 تاریخ پذیرش : 1402/03/18 تاریخ انتشار : 1403/12/29

کلید واژه: سلول حافظه ایستا, دسترسی تصادفی, ترانزیستور فین‌فت, مصرف توان,

چکیده مقاله :

ترانزیستور‌های اثر میدان (فین‌فت) به دلیل توانایی بالقوه در کنترل اثرات کانال کوتاه، جریان نشتی، تاخیر انتشار و اتلاف توان، جایگزین مناسبی برای ترانزیستور‌های معمولی فلزی-اکسید-نیمه هادی (ماسفت) می‌باشند. با توجه به اینکه حافظه‌های ایستا با دستیابی تصادفی، بیشترین فضای پردازنده‌های پیشرفته را اشغال می‌کنند، لذا عمده مصرف توان این پردازنده‌ها به این حافظه‌ها اختصاص می‌یابد. در سلول حافظه ایستا 6 ترانزیستوری رایج، هنگام خواندن و نوشتن، خازن‌های مربوط به خطوط بیت هردو باید بارگیری و تخلیه شوند. بنابراین قسمت عمده‌ای از مصرف توان، مربوط به این ساز‌و‌کار می‌باشد. در این تحقیق یک سلول حافظه 7 ترانزیستوری با استفاده از ترانزیستورهای فین‌فت با قابلیت نوشتن با استفاده از یکی از خطوط بیت پیشنهاد شده‌است. نتایج شیبه‌سازی با استفاده از نرم‌افزار اچ‌اس‌پایس و در فناوری 32 نانومتر نشان می‌دهد که مصرف توان این سلول در هنگام نوشتن زمانی که در سلول مقدار "0" ذخیره شده‌است، حداکثر به میزان %6/98 و هنگامی که در سلول مقدار "1" وجود دارد، به میزان %8/99 کاهش داشته‌است. همچنین میزان حاشیه امنیت در برابر نویز در حالت‌های آماده‌به‌کار و خواندن سلول به ترتیب برابر با 2025/0 و 2011/0 ولت می‌باشد.

چکیده انگلیسی:

Fin field-effect transistors (FinFETs) are good alternatives to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) because of their potential for controlling the effects of short channel, leakage current, propagation delay and power loss. Since SRAMs occupy most of the advanced processors’ space, main power consumption in these processors is attributed to these memories. In a common 6-transistor static random access memory (6T SRAM) cell, the capacitors of both bit lines must be charged and discharged when reading and writing tasks are performed. Thus, most of the power consumption is related to this mechanism. In this paper, 7-Transistor static random-access memory (7T SRAM) cell is proposed that is able to write using one of the bit lines. The results of simulation using HSPICE software and in 32 nm technology show that the power consumption of this cell during write operation when the value "0" is stored in the cell is at most 98.6% and it has decreased by 99.8% when the value "1" is present in the cell. Also, the amount of Static Noise Margin (SNM) in standby and cell reading modes is equal to 0.2025 and 0.2011 volts respectively.

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