طراحی و شبیه‌سازی یک تمام جمع‌کننده جدید در تکنولوژی نانو لوله‌ی کربنی با عملکرد بهینه

محورهای موضوعی : ادوات نیمه هادی

عباس اسدی آقبلاغی ¹ , مهران عمادی ²

1 - شرکت کوثر سپاهان، اصفهان
2 - دانشگاه آزاد اسلامی، مبارکه

تاریخ دریافت : 1393/04/18 تاریخ پذیرش : 1394/02/19 تاریخ انتشار : 1394/02/01

کلید واژه: نانو لوله‌ی کربنی, ترانزیستورهای نانو لوله‌ی کربنی, سلول ‌تمام جمع‌کننده, طراحی مدارهای مجتمع با مقیاس بزرگ,

چکیده مقاله :

مدار تمام جمع کننده، به دلیل توانایی در پیاده‌سازی چهار عمل اصلی محاسباتی (جمع، تفریق، ضرب و تقسیم) به عنوان یکی از مهمترین و پرکاربردترین بخش‌های اصلی پردازنده‌های دیجیتالی در طرّاحی مدارهای مجتمع، شناخته می‌شود. بدین منظور، در این مقاله تلاش شده است که سلول تمام جمع‌کننده‌ی جدیدی با بهره‌گیری از تکنولوژی ترانزیستورهای نانولوله‌ی کربنی، جهت دستیابی به مداری با عملکردی مناسب و توان مصرفی کم، ارائه گردد. طرح پیشنهادی از 12 ترانزیستور CNTFET که با استفاده از منطق ترانزیستورهای عبور به هم متصل شده‌اند، تشکیل شده است. ترانزیستورهای نانولوله‌ی کربنی در توان مصرفی و سرعت عملکرد، برتری قابل توجهی نسبت به ترانزیستورهایMOSFET از خود نشان می‌دهند. شبیه‌سازی طرح پیشنهادی، با استفاده از نرم افزار Hspice و بر مبنای مدل CNTFET، با ولتاژ اعمالی V65/0 در سه فرکانس و سه مقدار خازن بار متفاوت، انجام می‌شود و نتایج به دست آمده، برتری طرح پیشنهادی را نسبت به مدارهای نظیر ارائـه شده در مقالات پیشین، اثبـات می‌کند

چکیده انگلیسی:

The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and division. so, in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET) has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0.65V supply voltage. the simulations are done considering three different frequencies, and three different load capacitors. The simulation results, which demonstrated in tables and diagrams, proved the superiority of proposed design in terms of power consumption and performance (PDP) compared to the existing counterparts.

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