طراحی و شبیه سازی حافظه چهار ترانزیستوری و دو ممریستوری با کمترین توان مصرفی و حاصلضرب تاخیر در توان
محورهای موضوعی : انرژی های تجدیدپذیر
کرامت کرمی
1
,
سید محمد علی زنجانی
2
,
مهدی دولتشاهی
3
1 - دانشکده مهندسی برق- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران
2 - مرکز تحقیقات ریز شبکه های هوشمند- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران
3 - دانشکده مهندسی برق- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران
کلید واژه: حافظه غیرفرار, ممریستور, سلول4T2M, حاصلضرب تاخیر در توان,
چکیده مقاله :
ممریستور به عنوان عنصر اساسی حافظه های اصلی یا پنهان SRAM و DRAM،می تواند به صورت موثری زمان راه اندازی و توان مصرفی مدارها را کاهش دهد. غیر فرار بودن، چگالی بالای مدار نهایی و کاهش حاصل ضرب تاخیر در توان مصرفی PDp از حقایق قابل توجه مدارهای ممریستوری است که منجر به پیشنهاد سلول حافظه شامل چهار ترانزیستور و دو ممریستور (4T2M) در این مقاله شده است. به منظور شبیه سازی سلول حافظه پیشنهادی، طول ممریستورها 10 نانومتر و مقاومت حالت های روشن و خاموش آنها به ترتیب 250 اهم و 10 کیلو اهم انتخاب شده است. همچنین، ترانزیستورهای MOS سلول نیز توسط مدل CMOS PTM 32 نانومتر شبیه سازی شده اند. شبیه سازی در نرم افزار اچ-اسپایس و با تغذیه یک ولت و مقایسه آن با دو سلول شش ترانزیستوری متعارف (6T) و دو ترانزیستوری-دو ممریستوری (2T2M) نشان می دهد که استفاده از ممریستور سبب غیر فرار شدن سلول حافظه پیشنهادی و سلول 2T2M در زمان قطع ولتاژ تغذیه شده است، ضمن آن که مصرف توان مدار پیشنهادی نسبت به مدار 6T و 2T2M به ترتیب 8/99 درصد و 2/57 درصد کاهش یافته و حاصل ضرب متوسط تاخیر در توان نیز به ترتیب 4/99 درصد و 7/26 درصد بهبود یافته است؛ هرچند تاخیر نوشتن این سلول و سلول 2T2Mنسبت به سلول 6T به ترتیب 400 درصد و 218 درصد افزایش یافته است.
Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of memristor circuits, which has led to the suggestion of a memory cell including and four transistors and two memristors (4T2M) in this paper. In order to simulate the proposed memory cell, the length of memristors has been selected 10 nm, and their on/off state resistors have been selected 250 Ω and 10 KΩ respectively. In addition, the proposed memory cell MOS transistors are simulated by the 32 nm CMOS PTM model. Simulation in the HSPICE software with 1V supply voltage and comparison with two conventional six-transistor (6T) and two transistors-two memory (2T2M) cells show that the use of memristors has made the proposed memory cell and 2T2M cell non-volatile. Moreover, the power consumption of the proposed circuit has decreased by 99.8% and 57.2%, compared to the previous two circuits respectively, and the power average delay product has also improved by 99.4% and 26.7%, respectively; however, the writing delay of this cell and 2T2M cell increased by 400% and 218% compared to 6T cell, respectively.
[1] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, "A CNTFET universal mixed‐mode biquad active filter in subthreshold region", International Journal of RF and Microwave Computer‐Aided Engineering, vol. 28, no. 9, Article Number: e21574, Nov. 2018 (doi:10.1002/mmce.21574(.
[2] N. Shaarawy, M. Ghoneima, A.G. Radwan, "2T2M Memristor-based memory cell for higher stability RRAM modules", Proceeding of the IEEE/ISCAS, pp. 1418-1421, Lisbon, Portugal, May 2015 (doi: 10.1109/ISCAS.2015.7168909).
[3] A. Baghi-Rahin, V. Baghi-Rahin, "A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders", Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 13-22, Spring 2019 (in Persian).
[4] N. Dehabadi, R. Faghih-Mirzaee, "Ternary DCVS half adder with built-in boosters”, Journal of Intelligent Procedures in Electrical Technology, vol. 11, no. 42, pp. 41-56, Summer 2020(in Persian).
[5] A.M.S. Tosson, A. Neale, M. Anis, L. Wei, "8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design", Proceeding of the IEEE/GLSVLSI, pp. 239-244, Boston, MA, USA, May 2016 (doi: 10.1145/2902961.2903016).
[6] S. Pal, S. Bose, W.-H. Ki, A. Islam, "Design of power- and variability-aware nonvolatile RRAM cell using memristor as a memory element", IEEE Journal of the Electron Devices Society, vol. 7, pp. 701-709, July 2019 (doi: 10.1109/JEDS.2019.2928830).
[7] S. Bhatti, R. Sbiaa, A. Hirohata, H. Ohno, S. Fukami, S.N. Piramanayagam, "Spintronic based random access memory: A review", Materials Today, vol. 20, no. 9, pp. 530-548, Nov. 2017 (doi: 10.1016/j.mattod.2017.07.007).
[8] K. Eshraghian, K. Cho, O. Kavehei, S. Kang, D. Abbott, S.S. Kang, "Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1407-1417, Aug. 2011 (doi: 10.1109/TVLSI.2010.2049867).
[9] K. Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki, K. Noda, K. Matsui, S. Itoh, S. Masuoka, T. Horiuchi, A. Nakagawa, K. Shimogawa, H. Takahashi, "A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro", IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1631-1640, Nov. 2000 (doi: 10.1109/4.881209).
[10] I. Carlson, S. Andersson, S. Natarajan, A. Alvandpour, "A high density, low leakage, 5T SRAM for embedded caches", Proceedings of the IEEE/ESSCIR, pp. 215-218, Leuven, Belgium, Sept. 2004 (doi: 10.1109/ESSCIR.2004.1356656).
[11] G.M.S. Reddy, P.C. Reddy, "Design and implementation of 8k-bits low power SRAM in 180nm technology", Proc. Of the IMCECS, vol. 18, no. 2, pp. 1-8, March 2009.
[12] R.E. Aly, M.A. Bayoumi, "Low-power cache design using 7T SRAM cell", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 318-322, April 2007 (doi: 10.1109/TCSII.2006.877276).
[13] L. Wen, X. Cheng, K. Zhou, S. Tian, X. Zeng, "Bit-interleaving-enabled 8T SRAM with shared data-aware write and reference-based sense amplifier", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 63, no. 7, pp. 643-647, July 2016 (doi: 10.1109/TCSII.2016.2530881).
[14] M. Hemmati, M. Dolatshahi, S.M.A. Zanjani, "Design and optimization of non-volatile memory based on Memristor System", Proceeding of the IEEE/ICCKE, pp. 654-659, Mashhad, Iran, Oct. 2020 (doi: 10.1109/ICCKE50421.2020.9303681).
[15] I. Vourkas, G.C. Sirakoulis, "A novel design and modeling paradigm for memristor-based crossbar circuits", IEEE Trans. on Nanotechnology, vol. 11, no. 6, pp. 1151-1159, Nov. 2012 (doi: 10.1109/TNANO.2012.2217153).
[16] G. Papandroulidakis, A. Serb, A. Khiat, G. V. Merrett, T. Prodromakis, "Practical implementation of memristor-based threshold logic gates", IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3041-3051, Aug. 2019 (doi:10.1109/TCSI.2019.2902475).
[17] I. Vourkas, G. C. Sirakoulis, "Memristor-based nanoelectronic computing circuits and architectures", vol. 19: Springer, Switzerland, 2016 (ISBN: 978-3-319-22647-7).
[18] G. Papandroulidakis, I. Vourkas, N. Vasileiadis, G.C. Sirakoulis, "Boolean logic operations and computing circuits based on memristors", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 61, no. 12, pp. 972-976, Sept. 2014 (doi: 10.1109/TCSII.2014.2357351).
[19] S.S. Sarwar, S.A.N. Saqueb, F. Quaiyum, A. Rashid, "Memristor-based nonvolatile random access memory: hybrid architecture for low power compact memory design", IEEE Access, vol. 1, no. 23, pp. 29-35, May 2013 (doi: 10.1109/ACCESS.2013.2259891).
[20] V. Saminathan, K. Parasamivam, "Design and analysis of low power hybrid memristor-CMOS based distinct binary logic nonvolatile SRAM cell", Circuit and System, vol. 7, no. 8, pp. 119-127, March 2016 (doi: 10.4236/cs.2016.73012 ).
[21] M. N. Sakib, R. Hassan, S. Biswas, "A memristor-based 6T1M hybrid memory cell without state drift during successive read", Proceeding of the IEEE/ICECE, pp. 202-205, Dhaka, Dec. 2016 (doi: 10.1109/ICECE.2016.7853891).
[22] J. Singh, B. Raj, "Design and investigation of 7T2M-NVSRAM with enhanced stability and temperature impact on store/restore energy", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 27, no 6, pp. 1322-1328, June 2019 (doi: 10.1109/TVLSI.2019.2901032).
[23] C. Roy, A. Islam, "TG based 2T2M RRAM using Memristor as memory element", Indian Journal of Science and Technology. Paper, vol. 9, no. 33, pp. 123-137, 2016 (doi: 10.17485/ijst/2016/v9i33/99508).
[24] A. Ebrahimi, E. Kargaran, A. Golmakani, "Design and analysis of three new SRAM cells", Majlesi Journal of Electrical Engineering, vol. 6, no. 4, pp. 30-38, Dec. 2012.
[25] A. Rezaei, S.M.A. Zanjani, “Design and analysis of 2 memristor-based nonvolatile SRAM cells”, Journal of Novel Researches on Electrical Power, vol. 9, no. 2, pp. 47-56, Summer 2020 (in Persian).
[26] Z. Lin, Y. Wang, C. Peng, X. Wu, X. Li, J. Chen, "Multiple sharing 7T1R nonvolatile SRAM with an improved read/write margin and reliable restore yield", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 607-619, March 2020 (doi: 10.1109/TVLSI.2019.2953005).
[27] N. S. Soliman, M. E. Fouda, A. G. Radwan, "Memristor-CNTFET based ternary logic gates", Microelectronics journal, vol. 72, pp. 74-85, 2018 (doi: 10.1016/j.mejo.2017.12.008).
[28] C. Sun, K. Han, X. Gong, "Performance evaluation of static random access memory (SRAM) based on negative capacitance finFET", Proceeding of the IEEE/ICICDT, pp. 1-4, SUZHOU, China, 2019 (doi: 10.1109/ICICDT.2019.8790831).
[29] D. Batas, H. Fiedler, "A memristor SPICE implementation and a new approach for magnetic flux controlled memristor modeling", IEEE Trans. on Nanotechnology, vol. 10, no. 2, pp. 250-255, March 2011 (doi: 10.1109/TNANO.2009.2038051).
[30] Z. Kolka, D. Biolek, V. Biolkova, "Hybrid modelling and emulation of mem-systems", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 25, no. 3, pp. 216-225, May/June 2012 (doi: 10.1002/jnm.825).
[31] Y.V. Pershin, M.D. Ventra, "Spice model of memristive devices with threshold", Radio Engineering, vol. 22, no. 2, pp. 485-489, May 2013.
_||_[1] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, "A CNTFET universal mixed‐mode biquad active filter in subthreshold region", International Journal of RF and Microwave Computer‐Aided Engineering, vol. 28, no. 9, Article Number: e21574, Nov. 2018 (doi:10.1002/mmce.21574(.
[2] N. Shaarawy, M. Ghoneima, A.G. Radwan, "2T2M Memristor-based memory cell for higher stability RRAM modules", Proceeding of the IEEE/ISCAS, pp. 1418-1421, Lisbon, Portugal, May 2015 (doi: 10.1109/ISCAS.2015.7168909).
[3] A. Baghi-Rahin, V. Baghi-Rahin, "A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders", Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 13-22, Spring 2019 (in Persian).
[4] N. Dehabadi, R. Faghih-Mirzaee, "Ternary DCVS half adder with built-in boosters”, Journal of Intelligent Procedures in Electrical Technology, vol. 11, no. 42, pp. 41-56, Summer 2020(in Persian).
[5] A.M.S. Tosson, A. Neale, M. Anis, L. Wei, "8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design", Proceeding of the IEEE/GLSVLSI, pp. 239-244, Boston, MA, USA, May 2016 (doi: 10.1145/2902961.2903016).
[6] S. Pal, S. Bose, W.-H. Ki, A. Islam, "Design of power- and variability-aware nonvolatile RRAM cell using memristor as a memory element", IEEE Journal of the Electron Devices Society, vol. 7, pp. 701-709, July 2019 (doi: 10.1109/JEDS.2019.2928830).
[7] S. Bhatti, R. Sbiaa, A. Hirohata, H. Ohno, S. Fukami, S.N. Piramanayagam, "Spintronic based random access memory: A review", Materials Today, vol. 20, no. 9, pp. 530-548, Nov. 2017 (doi: 10.1016/j.mattod.2017.07.007).
[8] K. Eshraghian, K. Cho, O. Kavehei, S. Kang, D. Abbott, S.S. Kang, "Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1407-1417, Aug. 2011 (doi: 10.1109/TVLSI.2010.2049867).
[9] K. Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki, K. Noda, K. Matsui, S. Itoh, S. Masuoka, T. Horiuchi, A. Nakagawa, K. Shimogawa, H. Takahashi, "A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro", IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1631-1640, Nov. 2000 (doi: 10.1109/4.881209).
[10] I. Carlson, S. Andersson, S. Natarajan, A. Alvandpour, "A high density, low leakage, 5T SRAM for embedded caches", Proceedings of the IEEE/ESSCIR, pp. 215-218, Leuven, Belgium, Sept. 2004 (doi: 10.1109/ESSCIR.2004.1356656).
[11] G.M.S. Reddy, P.C. Reddy, "Design and implementation of 8k-bits low power SRAM in 180nm technology", Proc. Of the IMCECS, vol. 18, no. 2, pp. 1-8, March 2009.
[12] R.E. Aly, M.A. Bayoumi, "Low-power cache design using 7T SRAM cell", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 318-322, April 2007 (doi: 10.1109/TCSII.2006.877276).
[13] L. Wen, X. Cheng, K. Zhou, S. Tian, X. Zeng, "Bit-interleaving-enabled 8T SRAM with shared data-aware write and reference-based sense amplifier", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 63, no. 7, pp. 643-647, July 2016 (doi: 10.1109/TCSII.2016.2530881).
[14] M. Hemmati, M. Dolatshahi, S.M.A. Zanjani, "Design and optimization of non-volatile memory based on Memristor System", Proceeding of the IEEE/ICCKE, pp. 654-659, Mashhad, Iran, Oct. 2020 (doi: 10.1109/ICCKE50421.2020.9303681).
[15] I. Vourkas, G.C. Sirakoulis, "A novel design and modeling paradigm for memristor-based crossbar circuits", IEEE Trans. on Nanotechnology, vol. 11, no. 6, pp. 1151-1159, Nov. 2012 (doi: 10.1109/TNANO.2012.2217153).
[16] G. Papandroulidakis, A. Serb, A. Khiat, G. V. Merrett, T. Prodromakis, "Practical implementation of memristor-based threshold logic gates", IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3041-3051, Aug. 2019 (doi:10.1109/TCSI.2019.2902475).
[17] I. Vourkas, G. C. Sirakoulis, "Memristor-based nanoelectronic computing circuits and architectures", vol. 19: Springer, Switzerland, 2016 (ISBN: 978-3-319-22647-7).
[18] G. Papandroulidakis, I. Vourkas, N. Vasileiadis, G.C. Sirakoulis, "Boolean logic operations and computing circuits based on memristors", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 61, no. 12, pp. 972-976, Sept. 2014 (doi: 10.1109/TCSII.2014.2357351).
[19] S.S. Sarwar, S.A.N. Saqueb, F. Quaiyum, A. Rashid, "Memristor-based nonvolatile random access memory: hybrid architecture for low power compact memory design", IEEE Access, vol. 1, no. 23, pp. 29-35, May 2013 (doi: 10.1109/ACCESS.2013.2259891).
[20] V. Saminathan, K. Parasamivam, "Design and analysis of low power hybrid memristor-CMOS based distinct binary logic nonvolatile SRAM cell", Circuit and System, vol. 7, no. 8, pp. 119-127, March 2016 (doi: 10.4236/cs.2016.73012 ).
[21] M. N. Sakib, R. Hassan, S. Biswas, "A memristor-based 6T1M hybrid memory cell without state drift during successive read", Proceeding of the IEEE/ICECE, pp. 202-205, Dhaka, Dec. 2016 (doi: 10.1109/ICECE.2016.7853891).
[22] J. Singh, B. Raj, "Design and investigation of 7T2M-NVSRAM with enhanced stability and temperature impact on store/restore energy", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 27, no 6, pp. 1322-1328, June 2019 (doi: 10.1109/TVLSI.2019.2901032).
[23] C. Roy, A. Islam, "TG based 2T2M RRAM using Memristor as memory element", Indian Journal of Science and Technology. Paper, vol. 9, no. 33, pp. 123-137, 2016 (doi: 10.17485/ijst/2016/v9i33/99508).
[24] A. Ebrahimi, E. Kargaran, A. Golmakani, "Design and analysis of three new SRAM cells", Majlesi Journal of Electrical Engineering, vol. 6, no. 4, pp. 30-38, Dec. 2012.
[25] A. Rezaei, S.M.A. Zanjani, “Design and analysis of 2 memristor-based nonvolatile SRAM cells”, Journal of Novel Researches on Electrical Power, vol. 9, no. 2, pp. 47-56, Summer 2020 (in Persian).
[26] Z. Lin, Y. Wang, C. Peng, X. Wu, X. Li, J. Chen, "Multiple sharing 7T1R nonvolatile SRAM with an improved read/write margin and reliable restore yield", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 607-619, March 2020 (doi: 10.1109/TVLSI.2019.2953005).
[27] N. S. Soliman, M. E. Fouda, A. G. Radwan, "Memristor-CNTFET based ternary logic gates", Microelectronics journal, vol. 72, pp. 74-85, 2018 (doi: 10.1016/j.mejo.2017.12.008).
[28] C. Sun, K. Han, X. Gong, "Performance evaluation of static random access memory (SRAM) based on negative capacitance finFET", Proceeding of the IEEE/ICICDT, pp. 1-4, SUZHOU, China, 2019 (doi: 10.1109/ICICDT.2019.8790831).
[29] D. Batas, H. Fiedler, "A memristor SPICE implementation and a new approach for magnetic flux controlled memristor modeling", IEEE Trans. on Nanotechnology, vol. 10, no. 2, pp. 250-255, March 2011 (doi: 10.1109/TNANO.2009.2038051).
[30] Z. Kolka, D. Biolek, V. Biolkova, "Hybrid modelling and emulation of mem-systems", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 25, no. 3, pp. 216-225, May/June 2012 (doi: 10.1002/jnm.825).
[31] Y.V. Pershin, M.D. Ventra, "Spice model of memristive devices with threshold", Radio Engineering, vol. 22, no. 2, pp. 485-489, May 2013.
