FPGA Can be Implemented Using Advanced Encryption Standard Algorithm
محورهای موضوعی : journal of Artificial Intelligence in Electrical Engineeringکلید واژه: AES, Encryption, decryption, FPGA,
چکیده مقاله :
This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. This method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theAES InverseSub Bytes module and Inverse Mix columns module. As the S -box is implemented bylook-up-table in this design, the chip area and power can still be optimized. The new MixColumn transformation improves the performance of the inverse cipher and also reduces thecomplexity of the system that supports the inverse cipher. As a result this transformation hasrelatively low relevant diffusion power .This allows for scaling of the architecture towardsvulnerable portable and cost-sensitive communications devices in consumer and militaryapplications.
1]Daemen J., and Rijmen V, "The Design of
Rijndael: AES-the Advanced Encryption
Standard", Springer-Verlag , 2002
[2]FIPS 197, “Advanced Encryption Standard
(AES)”, November 26, 2001.
[3]Tessier, R., and Burleson, W.,
“Reconfigurable computing for digital signal
processing: a survey”, J.VLSI Signal Process,
2001, 28, (1-2), pp.7-27.
[4]Ahmad, N.; Hasan, R.; Jubadi, W.M;
“Design of AES S-Box using combinational
logic optimization”, IEEE Symposium on
Industrial Electronics & Applications
(ISIEA), pp. 696-699, 2010.
