روش جدید در امنیت سیستم های رمزنگاری توسط گیت های نامتوازن
محورهای موضوعی : پردازش چند رسانه ای، سیستمهای ارتباطی، سیستمهای هوشمند
سید حمیدرضا موسوی
1
,
مهدی صفائیان
2
,
امیر حسن احمدی قلعه
3
1 - استادیار، دانشکده مهندسی برق و کامپیوتر، واحد زنجان، دانشگاه آزاد اسلامی، زنجان، ایران.
2 - استادیار، دانشکده مهندسی برق و کامپیوتر، واحد هیدج، دانشگاه آزاد اسلامی، زنجان، ایران
3 - دانش آموخته کارشناسی ارشد، گروه برق، واحد زنجان، دانشگاه آزاد اسلامی، زنجان، ایران
کلید واژه: حملات تفاضلی توان, گیت, حلقه فاز قفل شده, اندازه گیری توان, استاندارد رمزنگاری پیشرفته,
چکیده مقاله :
امروزه اشتراک اطلاعات و انتقال ایمن آن بین سیستمهای مختلف الکترونیکی ضروری شدهاست. یکی از چالشهای مهم در این زمینه حملات کانال جانبی میباشد که با استفاده از تکنیکهای موجود سعی در بدست آوردن کلید رمزنگاری دارند. هدف از این پژوهش ارائه طرح جدیدی برای مقاوم‌سازی الگوریتم‌های رمزنگاری میباشد. در این طرح با به هم زدن توان مصرفی توسط دو عامل ارتقاء گیت‌های کلیدی و تزریق تصادفی تاخیر در اجرای بخش‌های مختلف از الگوریتم استاندارد رمزنگاری پیشرفتهAES ، میزان مقاومت این سامانه در مقابل حملات تفاضلی توان DPA افزایش یافته است. برای اصلاح گیت XOR از مدلی استفاده شده است که با وجود توان متغیر در زمانهای مختلف عملکردی ثابت و منطقی دارد. ترکیب گیت فوق با تاخیرهای تصادفی که توسط PLL در ناحیه گذرا ساخته می‌شود، مقاومت سیستم را بیشتر بهبود داده است. طرح فوق در تکنولوژی 65nm پیاده شده و نتایج حاصل از شبیه‌سازی در مقابل حملات تفاضلی توان نتایج قابل قبولی را نشان داده است. این طرح تنها هزینه سربار 33 درصد در فضای اشغالی و 25 درصد در توان مصرفی را به دنبال داشته است، و تنها سرعت عملکرد 3 درصد کم شده است در حالی که مقاومت تقریبا دو برابر شده است.
IntroductionNowadays, sharing information in communication systems and computers demands high levels of security. Side channel attacks are mainly considered as a main challenge in cryptographic systems which they are used as attacking techniques to break encrypted devices such as smart cards. The purpose of this research is introducing a new plan for strengthening on-chip encryption algorithms. The proposed plan is based on using Phase-Locked Loop (PLL) and enhanced XOR gate in Advanced Encryption Standard (AES) algorithm. In this approach, by disturbing the power consumption and time of execution for each different round of the algorithm, the encryption algorithm is protected against Differential Power Attacks (DPA). The proposed method has been implemented in TSMC 65nm technology in Cadence and the results show that the algorithm becomes immune against DPA using this method. As overheads, the silicon area and power consumption increased about 33% and 25%, respectively, whereas, the clock rate has been reduced less than 3%. MethodIn modern digital systems, if the data in the systems carries classified information, data encryption is unavoidable. For example, encryption in smart cards, portable electronic devices, mobile phones and remote control devices use encryption systems to deal with unauthorized intruders [1][2]. One of the requirements of today's electronic systems is high speed, low power consumption and information security. The basis of this method is the combination of the two characteristics of delay and power noise injection into the system using gates,ResultsThe comparison of the results in the simulation mode showed that the system has a good resistance against DPA attacksOne of the characteristics that exist to check the ability of retrofitting methods is the amount of hardware overhead and the imposition of additional power in the proposed retrofitting method. To check this issue, the hardware overhead and power consumption of the implemented method are presented in Table (2).DiscussionWith a reasonable number of power diagrams, so that compared to In the previous designs, the number of power diagrams has been almost doubled and the only overhead cost of the system is the increase in the volume of the occupied space by 33% and the power consumption by 20%.
[1] P. Bilski and W. Winiecki, “Multi-core implementation of the symmetric cryptography algorithms in the measurement system,” Meas. J. Int. Meas. Confed., vol. 43, no. 8, pp. 1049–1060, 2010.
[2] I. Hammad, K. El-Sankary, and E. El-Masry, “High-speed AES encryptor with efficient merging techniques,” IEEE Embed. Syst. Lett., vol. 2, no. 3, pp. 67–71, 2010.
[3] P. C. Kocher et al., “Differential Power Analysis,” Journal of Cryptographic Engineering. pp. 1–10, 1999.
[4] J. W. Lee, S. C. Chung, H. C. Chang, and C. Y. Lee, “Efficient power-analysis-resistant dual-field elliptic curve cryptographic processor using heterogeneous dual-processing-element architecture,” IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 1, pp. 49–61, 2014.
[5] Randolph M, Diehl W. Power side-channel attack analysis: A review of 20 years of study for the layman. Cryptography. 2020 Jun;4(2):15.
[6] T. Popp, E. Oswald, and S. Mangard, “Power Analysis Attacks and Countermeasures,” Des. Test Comput. IEEE, vol. 24, no. 6, pp. 535–543, 2007.
[7] U. Rührmair et al., “Efficient Power and Timing Side Channels for Physical Unclonable Functions.” pp. 476–492, 2014.
[8] R. Bevan, E. Knudsen, and B. Bp, “Ways to Enhance Differential Power Analysis,” Icisc 2002, vol. 1, pp. 327–342, 2002.
[9] S. Mangard, “A Simple Power-Analysis (SPA) Attack on Implementations of the AES Key Expansion,” Society, vol. 2587, pp. 343–358, 2002.
[10] X. Cui, R. Li, W. Wei, J. Gu, and X. Cui, “AHardware implementation of des with combined countermeasure against DPA,” in Proceedings of International Conference on ASIC, 2013.
[11] M. Masoumi, P. Habibi, A. Dehghan, M. Jadidi, and L. Yousefi, “Efficient implementation of power analysis attack resistant advanced encryption standard algorithm on side-channel attack standard evaluation board,” Int. J. Internet Technol. Secur. Trans., vol. 6, no. 3, p. 203, 2016.
[12] I. Verbauwhede and K. Tiri, “A Dynamic and Differential CMOS Logic with Signal-Independent Power Consumption to Withstand Differential Power Analysis,” 2008.
[13] Z. Y. and Z. X. WANG Pengjun, “Design of Two-phase SABL Flip-flop for Resistant DPA Attacks,” Chinese J. Electron., vol. 22, no. 4, pp. 833–837, 2013.
[14] K. Tiri and I. Verbauwhede, “A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation,” Proc. - Des. Autom. Test Eur. Conf. Exhib., vol. 1, pp. 246–251, 2004.
[15] K. Tiri, D. Hwang, A. Hodjat, and B.-C. Lai, “Prototype IC with WDDL and differential routing–DPA resistance assessment,” Cryptogr. Hardw. Embed. Syst. – CHES 2005, vol. 3659/2005, pp. 354–365, 2005.
[16] T. Popp and S. Mangard, “Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints,” pp. 172–186, 2005.
[17] Sim BY, Kwon J, Choi KY, Cho J, Park A, Han DG. Novel side-channel attacks on quasi-cyclic code-based cryptography. IACR Transactions on Cryptographic Hardware and Embedded Systems. 2019 Aug 9:180-212.
[18] J. J. A. Fournier, S. Moore, H. Li, R. Mullins, and G. Taylor, “Security Evaluation of Asynchronous Circuits,” Cryptogr. Hardw. Embed. Syst. - CHES 2003, 2003.
[19] Y. Lu, M. P. O’Neill, and J. V. McCanny, “FPGA implementation and analysis of random delay insertion countermeasure against DPA,” Proc. 2008 Int. Conf. Field-Programmable Technol. ICFPT 2008, pp. 201–208, 2008.
[20] C. Y. Liu, P.C., Chang, H.C. and Lee, “A low overhead DPA countermeasure circuit based on ring oscillators,” IEEE Trans. Circuits Syst. II, vol. 57, no. 7, pp. 546–550, 2010.
[21] S. M. Trimberger, Field-Programmable Gate Array Technology. 2012.
[22] J. S. and W. Y. TANG Wenyi, “Dual-Voltage Single-Rail Dynamic DPA-Resistant Logic Based on Charge Sharing Mechanism,” Chinese J. Electron., vol. 26, no. 5, pp. 899–905, 2017.
[23] Lou X, Zhang T, Jiang J, Zhang Y. A survey of microarchitectural side-channel vulnerabilities, attacks, and defenses in cryptography. ACM Computing Surveys (CSUR). 2021 Jul 13;54(6):1-37.
[24] U.~Meyer-Bäse, “Coherent Demodulation with {FPGA}s,” Lect. Notes Comput. Sci., vol. 1142, pp. 166–175, 1996.
[25] V. Rashtchi and H. Mousavi, “Countermeasure cryptography algorithm by PLL to FPGA,” tjee, vol. 3, no. 2, 2017.
[26] Kumar R, Liu X, Suresh V, Krishnamurthy HK, Satpathy S, Anders MA, Kaul H, Ravichandran K, De V, Mathew SK. A time-/frequency-domain side-channel attack resistant AES-128 and RSA-4K crypto-processor in 14-nm CMOS. IEEE Journal of Solid-State Circuits. 2021 Jan 28;56(4):1141-51.
[27] V. Rashtchi and H. Mousavi, “Strengthening AES Encryption Algorithms with an Improved Logic Topology,” Majlesi J. Electr. Eng., vol. 6, no. 3, 2018.
[28] C. Tokunaga and D. Blaauw, “Secure AES engine with a local switched-capacitor current equalizer,” Dig. Tech. Pap. - IEEE Int. Solid-State Circuits Conf., 2009.
[29] H. Wang, “AES-based security coprocessor IC in 0.18 µm CMOS with resistance to differential power analysis side channel attack,” Ieee Jssc, vol. 41, no. 4, pp. 781–791, 2006.
[30] A. Attaran and M. Mirhassani, “An embedded low-overhead PLL-based countermeasure against DPA side channel attack,” ISSCS 2015 - Int. Symp. Signals, Circuits Syst., 2015.
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