Comprehensive Study of the Third-order Charge Pump PLL Dynamic Behavior
محورهای موضوعی : Majlesi Journal of Telecommunication DevicesHanane Gholamnataj 1 , Habib Adrang 2
1 - Department of Electrical Engineering, Nour Branch, Islamic Azad University, Nour, Iran
2 - Department of Electrical Engineering, Nour Branch, Islamic Azad University, Nour, Iran
کلید واژه: en,
چکیده مقاله :
This paper provides useful equations for the analysis of loop dynamics specification such as damping ratio, overshoot and settling time in the third-order charge pump PLL with second-order loop filter. The presented analysis method is based on the approximation of the output phase step response using the step response of the second-order systems. In fact, the results can be used as an accurate approximation in the design and analysis of third-order PLL. The performance of this method has been verified in an interesting example using behavioral simulations in MATLAB. Simulations demonstrate a significant agreement between the simulated results of the actual PLL and the proposed approximated approach.
[1] I. Young, J. Greason, and K. Wong, “PLL clock generator with 5 to 10MHz of lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, no.11, pp. 1599–1607, Nov. 1992.
[2] H. Adrang, H. Miar Naimi, “Modeling of Jitter in Bang-Bang CDR with Fourier Series Analysis”, IEEE Transactions on Circuits and Systems I, vol. 60, no. 1, pp. 3-10, Jan. 2013.
[3] Dong Jiao, Bongjin Kim, Kim, C.H., “Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation”, IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 1634–1639, Oct. 2012.
[4] H. Rategh, H. Samavati, and T. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 780–787, May 2000.
[5] A. Ebrahimi, H. Miar Naimi, H. Adrang, “Remarks on Transient amplitude analysis of CMOS cross-coupled oscillator”, IEICE Transactions on Electronics, vol. E94-C, no. 2, pp. 231-239, Feb. 2011.
[6] S. Aouini, K. Chuai; G. W. Roberts, “Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT”, IEEE Transactions on Circuits and Systems I, vol. 59, no.1, pp. 66-79, Jan. 2012.
[7] A. Ebrahimi, and H. Miar Naimi, "Analytical Equations for Amplitude Analysis of MOS Colpitts Oscillator," International Journal of Electronics, Vol. 98, No. 7, pp. 883-900, July 2011.
[8] A. Ebrahimi and H. Miar Naimi, “An improvement on the analytical methods for amplitude analysis of the MOS Colpitts oscillator” in 2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), Oct. 2010.
[9] S. Miyazawa, R. Horita, K. Hase, K. Kato, and S. Kojima, “A BiCMOS PLL-based data separator circuit with high stability and accuracy,” IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 116–121, Feb. 1991.
[10] J. Hein and J. Scott, “z-domain model for discrete-time PLLs,” IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393–1400, Nov. 1988.
[11] F. Gardner, “Charge pump phase-lock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov 1980.
[12] I. Novof, J. Austin, R. Kelkar, D. Strayer, and S. Wyatt, “Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter,” IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1259–1266, Nov. 1995.
[13] J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Nov. 1996.
[14] L. A. H. Monterio D. N. Favaretto Filho, and J. R. C. Piqueira, “Bifurcation Analysis for Third-Order Phased-Locked Loops,” IEEE signal processing letters.,vol.1, no.5, pp.494-496 , May.2004.
[15] A. Carlosena, M. Ugarte, A. J. Lopez-Martin, “Loop Filter Approximation for PLLs” IEEE MWSCAS, 2008, pp. 21-24.
[16] A. Carlosena, A.M. Lazaro, “A Novel Design Method for Phased-Locked Loops of any Order and Type,” IEEE MWSCAS, 2006, pp. 569-573.
[17] H. Adrang, “A systematic procedure for analysis of third-order charge pump phase-locked loop (PLL),” Scientific Research and Essays, vol. 7, no. 2, pp. 190-198, Jan. 2012.
[18] H. Adrang and H. M. Naimi, “A Novel Method for Analysis and Design of Third-Order Charge Pump PLL,” IEEE ECCTD Conference, pp. 591-594, 2009.
[19] C. Cao, Y. Ding and K. O. Kenneth, “A 50-GHz Phase Locked Loop in 0.13-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1649-1656, Aug. 2007.
[20] J. R. Smith, “Modern Communication Circuits,” New York. McGraw-Hill, 1997.
[21] K. Ogata, “Modern Control Engineering,” Pearson Education. 2001.
