تفریق کننده های تقریبی توان پایین و قابل اطمینان برای کاربردهای پردازش تصاویر
فاطمه پولادی
1
(گروه مهندسی برق، ,واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران)
فرشاد پسران
2
(گروه مهندسی برق، ,واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران)
نبی اله شیری
3
(گروه مهندسی برق، ,واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران)
کلید واژه: تفریق کننده, محاسبات تقریبی, تکنولوژی CNTFET, تکنیک GDI,
چکیده مقاله :
در این مقاله دو تفریق کننده تقریبی جدید ارائه شده است. مدارهای پیشنهادی بر اساس تکنیک‌های ورودی انتشار گیت (GDI) و آستانه دینامیکی (DT) پیاده‌سازی شده‌اند و Proposed-1 و مدارProposed-2 نام‌گذاری شده‌اند. تفریق کننده Proposed-1 دارای 10 ترانزیستور است، در حالی که Proposed-2 دارای 12 ترانزیستور است. تفریق کننده ها توسط فناوری ترانزیستورهای اثر میدانی نانولوله کربنی 32 نانومتری (CNTFET) پیاده سازی می شوند. بررسی‌های مختلف اعمال شده و نشان‌دهنده راندمان و عملکرد بالای مدارها در شرایط مختلف بدون کاهش ولتاژ خروجی آنها است که ناشی از استفاده از آستانه دینامیکی (DT) در اجرای آنها است. مدارهای پیشنهادی از گیت های XOR و NOT استفاده می کنند که هر دو دارای 4 حالت از 8 حالت خطا هستند. تفریق‌کننده‌ها را می توان در یک تقسیم‌کننده غیر بازیابی بدون علامت با ساختارهای مختلف شامل عمودی، افقی، مربعی و مثلثی وغیره اجرا کرد ودر نهایت، از آنها در کاربردهای پردازش تصاویر برای تشخیص تفاوت دو تصویر اعم از تصاویر پزشکی یا استاندارد مورد استفاده قرار داد. نتایج شبیه‌سازی عملکرد بهتر مدارهای پیشنهادی، Proposed-1 و Proposed-2 را به ترتیب 88.36% و 83.25% در مقدار PDP صرفه‌جویی می‌کنند.
چکیده انگلیسی :
In this paper, two new approximate subtractors are presented. The proposed circuits are implemented based on gate diffusion input (GDI) and dynamic threshold (DT) techniques and are named Proposed-1 and Proposed-2. The Proposed-1 subtractor has 10 transistors, while Proposed-2 has 12 transistors. Subtractors are implemented by 32 nm carbon nanotube field effect transistor (CNTFET) technology. Various studies have been performed and show the high efficiency and performance of the circuits in different conditions without reducing their output voltage, which is caused by the use of DT in their implementation. The proposed circuits use XOR and NOT gates, both of which have 4 out of 8 error states. The presented subtractors can be implemented in an unsigned non-recovery divider with different structures including vertical, horizontal, square and triangular, etc., and finally, they can be used in image processing applications to detect the difference between two images, either medical or standard images. The simulation results show the better performance of the proposed circuits, Proposed-1 and Proposed-2 save PDP of 88.36% and 83.25%, respectively.
[1] W. Liu, F. Lombardi and M. Shulte, "A Retrospective and Prospective View of Approximate Computing [Point of View}," in Proceedings of the IEEE, vol. 108, no. 3, pp. 394-399, March 2020, doi: 10.1109/JPROC.2020.2975695.
[2] H. Jiang, F. J. H. Santiago, H. Mo, L. Liu and J. Han, "Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications," in Proceedings of the IEEE, vol. 108, no. 12, pp. 2108-2135, Dec. 2020, doi: 10.1109/JPROC.2020.3006451.
[3] A. Sadeghi, R. Ghasemi, H. Ghasemian and N. Shiri, "High Efficient GDI-CNTFET-Based Approximate Full Adder for Next-Generation of Computer Architectures," in IEEE Embedded Systems Letters, vol. 15, no. 1, pp. 33-36, March 2023, doi: 10.1109/LES.2022.3192530.
[4] M. Rafiee, Y. Sadeghi, N. Shiri and A. Sadeghi "An approximate CNTFET4:2 compressor based on gate
diffusion input and dynamic threshold," Electron. Lett., vol. 57, pp. 650-652, 2021, . doi: 10.1049/ell2.12221.
[5] A. Gorantla and P. Deepa, “Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications,” J Electron Test , vol. 35, pp. 901–907, 2019, doi: 10.1007/s10836-019-05837-5.
[6] L. Chen, J. Han, W. Liu and F. Lombardi, "On the Design of Approximate Restoring Dividers for Error-Tolerant Applications," in IEEE Transactions on Computers, vol. 65, no. 8, pp. 2522-2533, Aug. 2016, doi: 10.1109/TC.2015.2494005.
[7] F. Sabetzadeh, M. H. Moaiyeri and M. Ahmadinejad, "A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4200-4208, 2019, doi: 10.1109/TCSI.2019.2918241.
[8] H. Jiang, L. Liu, F. Lombardi and J. Han, “Adaptive approximation in arithmetic circuits: A low-power unsigned divider design,” in Design, Automation Test in Europe Conference Exhibition (DATE), March 2018, pp. 1411–1416, doi: 10.23919/DATE.2018.8342233.
[9] F. Bahrami, N. Shiri and F. Pesaran, “An efficient Imprecise 4:2 Compressor Using Gate Diffusion Input Supplemented with Dynamic Threshold,” Journal of Southern Communication Engineering, vol. 13, no. 50, pp. 1-10, 2023, doi: 10.30495/jce.2023.1987535.1203 (in Persian).
[10] T. Rashedzadeh, S.M. Riyazi and N. Cheraghi Shirazi, “Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25-36, Jun. 2021 (in Persian).
[11] M. Sayyaf, A. Ghasemi and R.Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, vol. 13, no. 49, pp. 105-112, 2022, doi: 10.30495/jce.2022.692834 (in Persian).
[12] K. M. Reddy, M. H. Vasantha, Y. B. Nithin Kumar and D. Dwivedi, "Design of Approximate Dividers for Error Tolerant Applications," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2018, pp. 496-499, doi: 10.1109/MWSCAS..8623909.
[13] R. Ferreira, M. Leme, M. Corrêa, L. Agostini, C. Diniz and B. Zatt, "Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, pp. 426-429, doi: 10.1109/ICECS46596.2019.8964783.
[14] K. V. Krishnan, A. Satish and P. R. Krishnan, “Design of energy efficient approximate subtractors and restoring dividers for error tolerant applications,” Microelectronics Journal, vol. 131, p. 105668, 2023, doi: 10.1016/j.mejo.2022.105668.
[15] N. Shiri, A. Sadeghi, M. Rafiee and M. Bigonah, "SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits," International Journal of Circuit Theory and Application, 2022, pp. 1- 26, doi: 10.1002/cta.3251.
[16] M. Rafiee, N. Shiri and A. Sadeghi, “Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing,” Circuits Syst Signal Process , vol. 41, pp. 4848–4885, 2022, doi: 10.1007/s00034-022-01997-6.
[17] M. Mirzaei and S. Mohammadi, "Process variation-aware approximate full adders for imprecision-tolerant applications," Computers & Electrical Engineering, vol. 87, 2020, p. 106761, doi: 10.1016/j.compeleceng.2020.106761.
[18] A. Morgenshtein, A. Fish and I. A. Wagner, "Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566- 581, 2002, doi: 10.1109/TVLSI.2002.801578.
[19] A. Sadeghi, N. Shiri and M. Rafiee, "High-Efficient, Ultralow-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications," Circuits Syst Signal Process , vol. 39, pp. 6247–6275, 2020, doi: 10.1007/s00034-020-01459-x.
[20] M. Rafiee, F. Pesaran, A. Sadeghi and N. Shiri, “An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications,” Microelectronics Journal, vol. 118, 2021, p. 105287, doi: 10.1016/j.mejo.2021.105287.
[21] G. Hills, C. Lau and A. Wright, "Modern microprocessor built from complementary carbon nanotube transistors," Nature , vol. 572, pp. 595–602, 2019, doi: 10.1038/s41586-019-1493-8.
[22] H. Jiang, C. Liu, L. Liu, F. Lombardi and J. Han, “A review, classification, and comparative evaluation of approximate arithmetic circuits,” ACM J Emerg Technol Comput Syst. (JETC), vol. 13, no. 4, p. 60, 2017, doi:10.1145/3094124.
[23] A. Darabi, M.R. Salehi and E. Abiri, “One-sided 10T static-random access memory cell for energy efficient and noise-immune internet of things applications,” International Journal of Circuit Theory and Applications, 2022, doi: 10.1002/CTA.3408.
[24] A. T. Mahani and P. Keshavarzian, “A novel energy-efficient and high speed full adder using CNTFET,” Microelectronics Journal, vol. 61, pp. 79-88, 2017, doi: 10.1016/j.mejo.2017.01.009.
[25] E. Adams, S. Venkatachalam and S. -B. Ko, "Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders," in IEEE Transactions on Computers, vol. 69, no. 4, pp. 468-474, April 2020, doi: 10.1109/TC.2019.2953751.
[26] F. Pooladi, F. Pesaran and N. Shiri. "Efficient GDI- based approximate subtractors for change detection in bio-image processing applications." Microelectronics Journal , vol. 135 , p. 105757, May 2023, doi: 10.1016/j.mejo.2023.105757.
[27] F. Bahrami, N. Shiri and F. Pesaran, “A New Approximate Sum of Absolute Differences Unit for Bioimages Processing,” IEEE Embedded Systems Letters. 2023, doi: 10.1109/LES.2023.3245020.
[28] F. Bahrami, N. Shiri and F. Pesaran, “Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing,” Computers and Electrical Engineering, vol. 108, p. 108729, 2023, doi: 10.1016/j.compeleceng.2023.108729.
_||_[1] W. Liu, F. Lombardi and M. Shulte, "A Retrospective and Prospective View of Approximate Computing [Point of View}," in Proceedings of the IEEE, vol. 108, no. 3, pp. 394-399, March 2020, doi: 10.1109/JPROC.2020.2975695.
[2] H. Jiang, F. J. H. Santiago, H. Mo, L. Liu and J. Han, "Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications," in Proceedings of the IEEE, vol. 108, no. 12, pp. 2108-2135, Dec. 2020, doi: 10.1109/JPROC.2020.3006451.
[3] A. Sadeghi, R. Ghasemi, H. Ghasemian and N. Shiri, "High Efficient GDI-CNTFET-Based Approximate Full Adder for Next-Generation of Computer Architectures," in IEEE Embedded Systems Letters, vol. 15, no. 1, pp. 33-36, March 2023, doi: 10.1109/LES.2022.3192530.
[4] M. Rafiee, Y. Sadeghi, N. Shiri and A. Sadeghi "An approximate CNTFET4:2 compressor based on gate
diffusion input and dynamic threshold," Electron. Lett., vol. 57, pp. 650-652, 2021, . doi: 10.1049/ell2.12221.
[5] A. Gorantla and P. Deepa, “Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications,” J Electron Test , vol. 35, pp. 901–907, 2019, doi: 10.1007/s10836-019-05837-5.
[6] L. Chen, J. Han, W. Liu and F. Lombardi, "On the Design of Approximate Restoring Dividers for Error-Tolerant Applications," in IEEE Transactions on Computers, vol. 65, no. 8, pp. 2522-2533, Aug. 2016, doi: 10.1109/TC.2015.2494005.
[7] F. Sabetzadeh, M. H. Moaiyeri and M. Ahmadinejad, "A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4200-4208, 2019, doi: 10.1109/TCSI.2019.2918241.
[8] H. Jiang, L. Liu, F. Lombardi and J. Han, “Adaptive approximation in arithmetic circuits: A low-power unsigned divider design,” in Design, Automation Test in Europe Conference Exhibition (DATE), March 2018, pp. 1411–1416, doi: 10.23919/DATE.2018.8342233.
[9] F. Bahrami, N. Shiri and F. Pesaran, “An efficient Imprecise 4:2 Compressor Using Gate Diffusion Input Supplemented with Dynamic Threshold,” Journal of Southern Communication Engineering, vol. 13, no. 50, pp. 1-10, 2023, doi: 10.30495/jce.2023.1987535.1203 (in Persian).
[10] T. Rashedzadeh, S.M. Riyazi and N. Cheraghi Shirazi, “Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25-36, Jun. 2021 (in Persian).
[11] M. Sayyaf, A. Ghasemi and R.Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, vol. 13, no. 49, pp. 105-112, 2022, doi: 10.30495/jce.2022.692834 (in Persian).
[12] K. M. Reddy, M. H. Vasantha, Y. B. Nithin Kumar and D. Dwivedi, "Design of Approximate Dividers for Error Tolerant Applications," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2018, pp. 496-499, doi: 10.1109/MWSCAS..8623909.
[13] R. Ferreira, M. Leme, M. Corrêa, L. Agostini, C. Diniz and B. Zatt, "Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, pp. 426-429, doi: 10.1109/ICECS46596.2019.8964783.
[14] K. V. Krishnan, A. Satish and P. R. Krishnan, “Design of energy efficient approximate subtractors and restoring dividers for error tolerant applications,” Microelectronics Journal, vol. 131, p. 105668, 2023, doi: 10.1016/j.mejo.2022.105668.
[15] N. Shiri, A. Sadeghi, M. Rafiee and M. Bigonah, "SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits," International Journal of Circuit Theory and Application, 2022, pp. 1- 26, doi: 10.1002/cta.3251.
[16] M. Rafiee, N. Shiri and A. Sadeghi, “Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing,” Circuits Syst Signal Process , vol. 41, pp. 4848–4885, 2022, doi: 10.1007/s00034-022-01997-6.
[17] M. Mirzaei and S. Mohammadi, "Process variation-aware approximate full adders for imprecision-tolerant applications," Computers & Electrical Engineering, vol. 87, 2020, p. 106761, doi: 10.1016/j.compeleceng.2020.106761.
[18] A. Morgenshtein, A. Fish and I. A. Wagner, "Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566- 581, 2002, doi: 10.1109/TVLSI.2002.801578.
[19] A. Sadeghi, N. Shiri and M. Rafiee, "High-Efficient, Ultralow-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications," Circuits Syst Signal Process , vol. 39, pp. 6247–6275, 2020, doi: 10.1007/s00034-020-01459-x.
[20] M. Rafiee, F. Pesaran, A. Sadeghi and N. Shiri, “An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications,” Microelectronics Journal, vol. 118, 2021, p. 105287, doi: 10.1016/j.mejo.2021.105287.
[21] G. Hills, C. Lau and A. Wright, "Modern microprocessor built from complementary carbon nanotube transistors," Nature , vol. 572, pp. 595–602, 2019, doi: 10.1038/s41586-019-1493-8.
[22] H. Jiang, C. Liu, L. Liu, F. Lombardi and J. Han, “A review, classification, and comparative evaluation of approximate arithmetic circuits,” ACM J Emerg Technol Comput Syst. (JETC), vol. 13, no. 4, p. 60, 2017, doi:10.1145/3094124.
[23] A. Darabi, M.R. Salehi and E. Abiri, “One-sided 10T static-random access memory cell for energy efficient and noise-immune internet of things applications,” International Journal of Circuit Theory and Applications, 2022, doi: 10.1002/CTA.3408.
[24] A. T. Mahani and P. Keshavarzian, “A novel energy-efficient and high speed full adder using CNTFET,” Microelectronics Journal, vol. 61, pp. 79-88, 2017, doi: 10.1016/j.mejo.2017.01.009.
[25] E. Adams, S. Venkatachalam and S. -B. Ko, "Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders," in IEEE Transactions on Computers, vol. 69, no. 4, pp. 468-474, April 2020, doi: 10.1109/TC.2019.2953751.
[26] F. Pooladi, F. Pesaran and N. Shiri. "Efficient GDI- based approximate subtractors for change detection in bio-image processing applications." Microelectronics Journal , vol. 135 , p. 105757, May 2023, doi: 10.1016/j.mejo.2023.105757.
[27] F. Bahrami, N. Shiri and F. Pesaran, “A New Approximate Sum of Absolute Differences Unit for Bioimages Processing,” IEEE Embedded Systems Letters. 2023, doi: 10.1109/LES.2023.3245020.
[28] F. Bahrami, N. Shiri and F. Pesaran, “Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing,” Computers and Electrical Engineering, vol. 108, p. 108729, 2023, doi: 10.1016/j.compeleceng.2023.108729.
