یک فشرده‌ساز تقریبی 4 به 2 با استفاده از ورودی گیت انتشار تکمیل شده با آستانه دینامیکی
محورهای موضوعی : مدارهای مجتمع الکترونیک
فروزان بهرامی
1
(گروه مهندسی برق ، دانشکده فنی و مهندسی، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران.)
نبی اله شیری
2
(گروه مهندسی برق ، دانشکده فنی و مهندسی، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران.)
فرشاد پسران
3
(گروه مهندسی برق ، دانشکده فنی و مهندسی، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران.)
کلید واژه: محاسبات تقریبی, CNTFET, GDI, کمپرسور تقریبی,
چکیده مقاله :
محاسبات تقریبی یک مفهوم طراحی جدید می باشد که بر مبنای یک داد و ستد بین عملکرد پارامترهای مداری و دقت استوار می باشد. مدارهای تقریبی در کابردهایی که مقاوم در برابر خطا هستند نقش بسیار مفیدی دارند یکی از این کاربردها پردازش تصویر می باشد. این مقاله یک کمپرسور 4-2 تقریبی با 12 ترانزیستور را معرفی می کند. کمپرسور پیشنهادی توان تلفاتی پایینی داشته و ولتاژ خروجی آن دارای سوئینگ کامل می باشد، این ویژگیهای ها ناشی از استفاده همزمان از تکنیکهای GDI و DT می باشد. مدار پیشنهادی با تکنولوژی 16 نانومتر CNTFET پیاده سازی شده که مساحت بسیار پایینی را اشغال می کند. با توجه به نتایج شبیه سازی، کمپرسور تقریبی 4-2 توان تلفاتی و PDP بسیار پایینی را نشان می دهد که این مقادیر در مقایسه با نمونه دقیق آن به ترتیب دارای کاهش 95.18% و 95.27% می باشند. مدار پیشنهادی از نظر سایر ویژگیهای مدارهای تقریبی مانند فاصله خطا، میانگین فاصله خطا و میانگین نرمالیزه شده فاصله خطا نیز مورد بررسی قرار گرفته است. نتایج شبیه سازی شایستگی های مدار پیشنهادی رابه ویژه برای کاربردهای پردازش سیگنالهای دیجیتال تایید می کند.
Approximate computing is a new design concept that causes a trade-off between circuitry performance and accuracy. The approximate circuits are more useful in error-resilient applications, like image processing. This paper introduces a new imprecise 4:2 compressor with 12 transistors. The presented compressor exhibits low power consumption and provides full-swing outputs, due to the utilization of gate diffusion input and dynamic threshold techniques. The implementation of this compressor using a 16 nm carbon nanotube field-effect transistor (CNTFET) technology yields a minimum area. According to the simulation results, the suggested imprecise 4:2 compressor shows a significant reduction in power consumption and power-delay-product (PDP) compared to the precise 4:2 compressor, with a reduction of 95.18% and 95.27%, respectively. Also, the compressor is evaluated regarding the approximate figure of merits like error rate, mean error distance, and normalized mean error distance. The simulation results affirm the priority of the suggested circuit, especially in digital signal processing.
[1] Q. Xu, T. Mytkowicz and N. S. Kim, “Approximate computing: A survey,” IEEE Des. Test., vol. 33, no. 1, pp. 8–22, Feb. 2016, doi: 10.1109/MDAT.2015.2505723.
[2] A. Sadeghi, N. Shiri and M. Rafiee, "High-Efficient, Ultra Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications," Circuits Syst Signal Process , vol. 39, pp. 6247–6275, 2020, doi: 10.1007/s00034-020-01459-x.
[3] F. Bahrami, N. Shiri and F. Pesaran, “A New Approximate Sum of Absolute Differences Unit for Bioimages Processing,” IEEE Embedded Systems Letters, Feb. 2023, doi: 10.1109/LES.2023.3245020.
[4] M. Rafiee, Y. Sadeghi, N. Shiri and A. Sadeghi, "An approximate CNTFET 4:2 compressor based on gate diffusion input and dynamic threshold,". Electron. Lett, vol. 57, pp. 650-652, 2021, doi: 10.1049/ell2.12221.
[5] T. Rashedzadeh, S.M. Riyazi and N. C Shirazi, “Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25-36, Jun. 2021. (in persian).
[6] M. Sayyaf, A. Ghasemi and R. Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, 2022, doi:10.30495/jce.2022.692834, (in persian).
[7] A. Momeni, J. Han, P. Montuschi and F. Lombardi, “Design and analysis of approximate compressors for multiplication,” IEEE Trans. Comput., vol. 64, no. 4, pp. 984–994, Apr. 2015, doi: 10.1109/TC.2014.2308214.
[8] S. Venkatachalam and S.-B. Ko, “Design of power and area efficient approximate multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 5, pp. 1782–1786, May 2017, doi: 10.1109/TVLSI.2016.2643639.
[9] M. Ha and S. Lee, “Multipliers with approximate 4–2 compressors and error recovery modules,” IEEE Embedded Syst. Lett., vol. 10, no. 1, pp. 6–9, Mar. 2018, doi: 10.1109/LES.2017.2746084.
[10] O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, “Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 4, pp. 1352–1361, Apr. 2017, doi: 10.1109/TVLSI.2016.2643003.
[11] M. Ahmadinejad, M. H. Moaiyeri and F. Sabetzadeh, “Energy and area efficient imprecise compressors for approximate multiplication at nanoscale,” AEU-Int. J. Electron. Commun., vol. 110, Art. no. 152859, Oct. 2019, doi: 10.1016/j.aeue.2019.152859.
[12] A. G. M. Strollo, et al, “Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers,” IEEE Trans. Circuits Syst. Regul. Pap., vol. 67, no. 9, pp. 3021–3034, 2020, doi: 10.1109/TCSI.2020.2988353.
[13] A. Morgenshtein, A. Fish and I. A. Wagner, "An efficient implementation of D-Flip-Flop using the GDI technique," IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, Canada, 2004, pp. II-673, doi: 10.1109/ISCAS.2004.1329361.
[14] H. Arfavi, S.M. Riyazi and R. Hamzehyan, “Evaluation of temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method,” Journal of Southern Communication Engineering, 2023, doi: 10.30495/jce.2023.1973764.1197, (in persian).
[15] F. Pooladi, F. Pesaran and N. Shiri, "Efficient GDI-based approximate subtractors for change detection in bio-image processing applications," Microelectronics Journal , vol. 135, p. 105757, May. 2023, doi: 10.1016/j.mejo.2023.105757.
[16] F. Bahrami, N. Shiri and F. Pesaran, “Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing,” Computers and Electrical Engineering, vol. 108, p. 108729, May 2023, doi: 10.1016/j.compeleceng.2023.108729.
_||_[1] Q. Xu, T. Mytkowicz and N. S. Kim, “Approximate computing: A survey,” IEEE Des. Test., vol. 33, no. 1, pp. 8–22, Feb. 2016, doi: 10.1109/MDAT.2015.2505723.
[2] A. Sadeghi, N. Shiri and M. Rafiee, "High-Efficient, Ultra Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications," Circuits Syst Signal Process , vol. 39, pp. 6247–6275, 2020, doi: 10.1007/s00034-020-01459-x.
[3] F. Bahrami, N. Shiri and F. Pesaran, “A New Approximate Sum of Absolute Differences Unit for Bioimages Processing,” IEEE Embedded Systems Letters, Feb. 2023, doi: 10.1109/LES.2023.3245020.
[4] M. Rafiee, Y. Sadeghi, N. Shiri and A. Sadeghi, "An approximate CNTFET 4:2 compressor based on gate diffusion input and dynamic threshold,". Electron. Lett, vol. 57, pp. 650-652, 2021, doi: 10.1049/ell2.12221.
[5] T. Rashedzadeh, S.M. Riyazi and N. C Shirazi, “Analysis of the effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25-36, Jun. 2021. (in persian).
[6] M. Sayyaf, A. Ghasemi and R. Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, 2022, doi:10.30495/jce.2022.692834, (in persian).
[7] A. Momeni, J. Han, P. Montuschi and F. Lombardi, “Design and analysis of approximate compressors for multiplication,” IEEE Trans. Comput., vol. 64, no. 4, pp. 984–994, Apr. 2015, doi: 10.1109/TC.2014.2308214.
[8] S. Venkatachalam and S.-B. Ko, “Design of power and area efficient approximate multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 5, pp. 1782–1786, May 2017, doi: 10.1109/TVLSI.2016.2643639.
[9] M. Ha and S. Lee, “Multipliers with approximate 4–2 compressors and error recovery modules,” IEEE Embedded Syst. Lett., vol. 10, no. 1, pp. 6–9, Mar. 2018, doi: 10.1109/LES.2017.2746084.
[10] O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, “Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 4, pp. 1352–1361, Apr. 2017, doi: 10.1109/TVLSI.2016.2643003.
[11] M. Ahmadinejad, M. H. Moaiyeri and F. Sabetzadeh, “Energy and area efficient imprecise compressors for approximate multiplication at nanoscale,” AEU-Int. J. Electron. Commun., vol. 110, Art. no. 152859, Oct. 2019, doi: 10.1016/j.aeue.2019.152859.
[12] A. G. M. Strollo, et al, “Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers,” IEEE Trans. Circuits Syst. Regul. Pap., vol. 67, no. 9, pp. 3021–3034, 2020, doi: 10.1109/TCSI.2020.2988353.
[13] A. Morgenshtein, A. Fish and I. A. Wagner, "An efficient implementation of D-Flip-Flop using the GDI technique," IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, Canada, 2004, pp. II-673, doi: 10.1109/ISCAS.2004.1329361.
[14] H. Arfavi, S.M. Riyazi and R. Hamzehyan, “Evaluation of temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method,” Journal of Southern Communication Engineering, 2023, doi: 10.30495/jce.2023.1973764.1197, (in persian).
[15] F. Pooladi, F. Pesaran and N. Shiri, "Efficient GDI-based approximate subtractors for change detection in bio-image processing applications," Microelectronics Journal , vol. 135, p. 105757, May. 2023, doi: 10.1016/j.mejo.2023.105757.
[16] F. Bahrami, N. Shiri and F. Pesaran, “Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing,” Computers and Electrical Engineering, vol. 108, p. 108729, May 2023, doi: 10.1016/j.compeleceng.2023.108729.
