A Smart Noise-Coupling Technique for low power DT-Σ∆ Modulators
محورهای موضوعی : مهندسی هوشمند برقHabibeh Fakhraie 1 , Tohid Moosazadeh 2 , Reza Sabbaghi-nadooshan 3 , Alireza Hassanzadeh 4
1 - Department of Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran
2 - Department of Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran
3 - Department of Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran
4 - ECE Department, Shahid Beheshti University, Tehran, Iran
کلید واژه: Single-Loop Σ Δ modulators, NTF order, noise-coupling (NC), AFF, SNDR,
چکیده مقاله :
In this paper, a new method for extending and relaxing the noise-coupling (NC) technique is proposed to enhance the noise-shaping order without adding the number of integrators. The noise-shaping order of the introduced ∑∆ modulator whit applying a second-order noise-coupling technique is enhanced and its performance with optimizing the noise transfer function (NTF) zeros is improved. Also, by removing the analog adder at feedforward path and transferring it to a new feedback branch before the last integrator and adding second-order NC path can be decreased the input voltage swing to the quantizer. Thus, by improving the modulator resolution, power consumption can be reduced. Mathematical analyses and behavioural simulation results confirm the effectiveness of the new NC method. To examine its performance, a 2nd-order single loop ΣΔ modulator was designed. The new noise-coupling method is used to achieve the three-order noise shaping to increase the resolution with low complexity and low-power. The results show an outstanding improvement in signal-to-noise and distortion ratio (SNDR) compared to the conventional structure.
International Journal of Smart Electrical Engineering, ISSN: 2251-9246
EISSN: 2345-6221
A Smart Noise-Coupling Technique for low power DT-Σ∆ Modulators
Habibeh Fakhraie1, Tohid Moosazadeh 2*, Reza Sabbaghi-nadooshan 3, Alireza Hassanzadeh4
1Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran, habibehfakhraee@yahoo.com
2Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran, t.mousazadeh@iauctb.ac.ir
3Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran, r_sabbaghi@iauctb.ac.ir
4ECE Department, Shahid Beheshti University, Tehran, Iran, hassanzade_5@yahoo.com
*Corresponding author
Abstract
In this paper, a new method for extending and relaxing the noise-coupling (NC) technique is proposed to enhance the noise-shaping order without adding the number of integrators. The noise-shaping order of the introduced ∑∆ modulator whit applying a second-order noise-coupling technique is enhanced and its performance with optimizing the noise transfer function (NTF) zeros is improved. Also, by removing the analog adder at feedforward path and transferring it to a new feedback branch before the last integrator and adding second-order NC path can be decreased the input voltage swing to the quantizer. Thus, by improving the modulator resolution, power consumption can be reduced. Mathematical analyses and behavioural simulation results confirm the effectiveness of the new NC method. To examine its performance, a 2nd-order single loop ΣΔ modulator was designed. The new noise-coupling method is used to achieve the three-order noise shaping to increase the resolution with low complexity and low-power. The results show an outstanding improvement in signal-to-noise and distortion ratio (SNDR) compared to the conventional structure.
Keywords: Single-Loop ΣΔ modulators, NTF order, noise-coupling (NC), AFF, SNDR.
1. Introduction
Today, high-performance and low-power electronic systems in analog to digital convertors (ADCs) new structures have attracted the attention of researchers. Sigma-delta (Σ∆) ADCs with high resolution and low power dissipation are main elements in electronic systems and medical devices. Sigma-Delta (ΣΔ) modulators achieve the high-SNDR with using oversampling and noise-shaping techniques. Since the increasing the oversampling ratio (OSR) enhances power consumption so enhancing the number of quantizer bits and noise-shaping order are two popular strategies for high-SNDR in the ΣΔ modulators [1].
The noise coupling (NC) technique has been proposed to improve the order of noise-shaping while reducing the number of integrators [2-4]. Compared to a conventional structure, the K-order noise-coupling technique can stash K-integrators with the same noise-shaping ability. Beside, the low-distortion input feedforward (IFF)-ΣΔ structure, the input signal is directly added before the quantizer thus reducing the output swing of the integrators [5].
In this paper, a resolution-enhanced DT 2nd-order single-loop Σ∆ modulator is presented using a first and second-order NC and AFF techniques. The introduced structure with NC new path, by removing the active adder before the quantizer and transferring it to a new feedback branch before the last integrator and adding second-order noise-coupling path can be decreased the input voltage swing to the quantizer. So the power consumption is reduced without changing the NTF order. Also, in proposed modulator is created one loop delay (z-1) from modulator output into the newly branch to stabilize the loop feedback due to the deletion of analog adder.
The organization of the paper is as follows: In Section 2, the structure of the proposed single-loop sigma-delta modulator is introduced. The mathematical analysis prove the effectiveness of the proposed modulator. The system-level results and op-amp non-ideality analysis of the proposed modulator are presented in Section 3. The SC circuit-level considerations and conclusion are presented in Sections 4. and Sections 5.
2. The Proposed Structure
In a single-loop Σ∆ modulator, The decrease in SNDR due to the less in OSR can be compensated by increasing the number of loop filter integrators and/or the resolution of the internal N-bit quantizer [6]. Figure 1 shows a general noise-coupling technique in a single-loop Σ∆ modulators. In this structure the quantization noise is delayed then feedback to the quantizer input [7]. Thus, the output signal of quantizer includes its input signal and a quantization noise that is shaped by (1-z-1)NTF(z). This minor change spins a conventional quantizer into a noise-shaping quantizer, which improves the NTF order by maintaining the stability of the modulator. For C(z)=z-1, output signal is as following:
(1)
Where STF and NTF are the signal and noise transfer functions, respectively. In this structure, the quantization noise is combined with a delay cell and applied to the quantizer input so first-order noise-shaping is added to NTF. For the first-order noise-coupling technique, the modulator can be saved one integrator. For C(z)=2z-1-z-2, modulator output achieves a second-order noise-shaping.
(2)
A second-order noise coupling scheme to achieve high-resolution and low-power dissipation [8].
Fig. 1 General block diagram of the AFF Noise-Coupling Σ∆ architecture.
Also, The IFF path connects the input signal directly to the input quantizer and reduces the needed swing for integrators output because the integrators analysis the quantization noise instead of input signal. The IFF path is performed using analog feedforward (AFF) path [10] or digital feedforward (DFF) [11]. The AFF path execution needs an active or a passive adder [9]. However, adding AFF and noise-coupling paths directly to the quantizer input increases the input voltage swing of the quantizer which reduces the effective gain of the quantizer and its internal resolution. In the following, the proposed NC method is presented in a single-loop Σ∆ structure to solve general noise-coupling path problems.
An AFF implementation of a conventional 2nd-order single-loop DT-Σ∆ modulator is shown in Fig. 2. The output of this structure is given by:
(3)
Fig. 2 Conventional 2nd-order single-loop Σ∆ modulator with AFF
Fig. 3 Single-loop Σ∆ modulator with AFF and 1st-order NC techniques.
The overall output of the modulator is given by:
Fig.4 shows the proposed single-loop Σ∆ modulator structure with second-order NC path to replace Fig.3 structure. This architecture removes the active adder before the quantizer and creates one loop delay (z-1) from modulator output into the newly branch to stabilize the feedback loop, and provides three-order noise-shaping for EQ with second-order NC technique.
In the introduced modulator, by removing the analog adder at feedforward path and transferring it to a new feedback branch before the last integrator and adding second-order NC path can be decreased the input voltage swing to the quantizer so the power consumption without changing the noise-shaping order is reduced. The proposed structure increase the SNDR about 6 dB compared to the structure of Fig. 3 due to the increase the effective gain of the quantizer and its internal resolution. Also, this structure diminishes the power consumption by deleting the analog adder, especially in a multi-bit quantizers.
The proposed modulator main blocks are AFF path, loop filters, N-bit quantizer and new noise-coupling path. This design focuses on reducing the hardware complexity of the structure for high performance and reducing power consumption by removing the analog adder.
Fig. 4 The proposed Σ∆ modulator with NC technique
(5)
Here, STF is unity and NTF has three zeros at z = 1. In order to improve the noise-coupling path and increase the resolution of the modulator without the instability effect at the quantizer, the coupling-noise path transfer function with high-order can be applied. If new noise-coupling path transfer function be (2z-1-3z-2+z-3), the overall output of the modulator with matching between loop filter and NC path is given by:
(6)
3. System-Level Implementation
behavioral simulations have been performed using MATLAB SIMULINK to prove the performance of the proposed ∑∆ structure. For comparison purpose, the conventional single-loop modulator shown in Fig. 2 and its first-order noise coupled version shown in Fig. 3 are simulated. The OSR, signal bandwidth (BW), and sampling frequency fs, were selected 16, 5 MHz, and 160 MHz, respectively. A 4-bit quantizer was used (N = 4). Figure. 5 displays the output power spectral density (PSD) of the introduced structure. For a 0.166 MHz input signal, the SNDR and ENOB are 94.6 dB, 15.43 bits, respectively. Figure 6 demonstrates the comparison of the PSD of the introduced structure with the mentioned two structures. The simulated SNDR versus the input signal amplitude is indicated in Fig. 7.
Fig. 5: Output PSD of the proposed modulator.
Fig. 6: Output PSD of the proposed, conventional and first-order NC structures.
Fig. 7: SNDR versus the input signal amplitude.
To investigate the mismatch in the introduced structure, with assuming β is mismatch factor between loop filter and noise-coupling path, the overall NTF will be as following:
(7)
Here, NTF has two zero at z=1 and one zero at z=β that is inside a single circle. Figure 8 shows output PSD of the proposed modulator according to mismatch and well-match in NC path. The system simulation result shows the SNDR is decreased 4 dB compare to the well-matching.
Fig. 8: Output PSD of the proposed modulator with and without paths’ mismatch.
3.1. The integrators’ non-idealities analyses
The non-ideal parameters of the integrators including finite op-amp gain, finite slew rate, and finite gain bandwidth (GBW) for the introduced modulator are simulated and compared with other structures. To make a fair comparison, all structures were simulated for the same OSR, BW, and fs mentioned above. Variations in SNDR based on circuit non-idealities are represented in Fig. 9. The minimum gain required for the op-amp in the last integrator in the proposed modulator is 30 dB. Figure 9 indicates that the op-amp gain requirement for the introduced structure is lower than of other structures, while the required GBW and slew rate are approximately equal.
(a)
(b)
(c)
Fig. 9: The SNDR variation vs. a) op-amp gain;
b) slew rate; c) GBW.
3.2. The impact of the N-bit DAC
The application of N-bit quantizers in ΣΔ modulators improve the modulator resolution. But N-bit quantizers need linear N-bit DAC, which must be equal to the accuracy of the whole linear modulator. The best technique for multi-bit DAC linearization is data weighted average (DWA) [15]. Since the effect of the DAC nonlinearity appears in the modulator input without noise-shaping so the DWA linearization technique is used. Fig. 10 shows the simulated output PSD of the modulator with and without DWA technique. This way, 65.4 dB SNDR of the modulator with real DAC is increased to 93.3 dB when the DWA technique is applied which is only about 1.3 dB less than the case when an ideal DAC is applied.
Fig. 10: Output PSD of the introduced structure for a nonlinear DAC and DAC with DWA technique.
Table 1. shows a comparison of system-level results including SNDR, op-amps non-ideal parameters for the proposed modulator with other modulators. The results mark the efficiency of the introduced structure compared to other structures. As the comparison table shows, the SNDR of the proposed structure is increased, due to the reduction of the input signal VFS to the quantizer, which increases the effective gain and its internal resolution.
Table 1. Comparison of the proposed 2nd-order single loop modulator with other two modulators.
| Conventional (Fig. 2) | AFF-1st- NC (Fig. 3) | The proposed (Fig. 4) |
SNDR (dB) | 72.3 | 88.3 | 94.6 |
ENOB (bits) | 11.72 | 14.30 | 15.43 |
Opamp Gain (dB) | 40 | 40 | 30 |
Slew Rate (V/S) | 5×108 | 5×108 | 5×105 |
GBW (MHz) | 2 ×102 | 2×102 | 2×102 |
Quantizer input swing | 0.95 | 0.95 | 0.65 |
NO. of integrators | 2 | 2 | 2 |
Noise-shaping order | 2 | 3 | 3 |
4. SC circuit-level considerations
The proposed second-order noise-coupling sigma delta modulator can be implemented by switched-capacitor (SC) circuit shown in Fig. 11. To implement the 4-bit DAC, 15-unit capacitors can be shared with the input sampling capacitors. Thus, the first integrator feedback gain does not decline, which results in less op-amp power consumption. The second integrator has four inputs, the first integrator output, Vi input signal AFF path, the z-1 delay and NC path. One delay unit of the second-order NC path, z-1, is combined with 1/(1-z-1) to form a delaying integrator. Two similar imprints of CNo and CNe capacitors are applied to enforcement the NC path with two sample delays of z-2 [24]. Each of these capacitors samples the output of the third integrator at even/odd sampling phases, holds it for 1.5 of a clock period, and then transmits it to the output of the second integrator. Since the integral output is constant until the end of the next sampling phase, 0.5 of a clock period later, two complete cycle delays are realized from the output of the third integrator to the output of the second integrator. By properly assigning the clock phases φ1o,e and φ2o,e , the z-2 delay is performed.
Table 2 compares the system-level results of the proposed modulator with other reported modulators. The results prove the effectiveness of the introduced structure than the other structures. Note that this SNDR is achieved by 3 orders of noise-shaping at the 2-order Σ∆ modulator while the others have 3 orders of noise-shaping at the 3-order Σ∆ modulator. This alleviates the complexities of circuit design, as the proposed modulator requires fewer OTAs to design and fewer branches that relax the OTA specification, thus reducing circuit complexity and power consumption.
Fig. 11 Switched-capacitor circuit schematic of the proposed modulator
Table 2. Efficiency comparison of the proposed modulator with several reported modulators
THIS WORK | AFF-NC 3rd Single loop [13] | AFF- MASH 2-1 [23] | DFF-NC 2-1 MASH [24] | AFF-NC- 2-1 MASH [22] | Parameter |
94.6 15.43 98 160 16 5 2
| 92 14.9 95 160 16 5 3 | 77.1 12 78.5 120 12 5 3 | 106 17.4 110 160 8 10 3 | 98.8 16 99 160 8 10 3 | SNDR [dB] ENOB [Bits] DR [dB] Sampling Rate (MHz) Oversampling Ratio Signal Bandwidth (MHz) NO. Of Integrators |
5. Conclusion
An effective noise coupling architecture is presented for ΣΔ modulators. The introduced modulator is less sensitive to finite op-amp DC gain effects and it is proper choice for wideband and high accuracy applications, combined with low power dissipation. By applying the second-order NC technique to a new feedback branch before the last integrator and NTF zeros optimization can achieve the high-order noise shaping and high-resolution. Thus the proposed modulator improves the SNDR and relaxes circuit-level implementation with reducing the analog block compared to the conventional modulator.
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