Congestion- and Energy-aware Run-time Task Mapping for Network-on-Chip Architecture
Subject Areas :mohammad ahmadipour 1 , Farhad Rad 2 * , Davood Heidarnasab 3
1 - Faculty of Engineering, Yasuj Branch, Islamic Azad University, Yasuj, Iran
2 - Faculty of Engineering, Yasuj Branch, Islamic Azad University, Yasuj, Iran
3 - Faculty of Engineering, Kazerun Branch, Islamic Azad University, Kazerun, Iran
Keywords: Network on chip, task mapping, particle swarm optimization,
Abstract :
Today, with the advancement of semiconductor technology, the number of processing components on the chip has increased. Networks on-chip or NoC has been proposed as an efficient and scalable communication scheme within chips to overcome bus problems. One of the major challenges for NoCs is mapping tasks on processing cores. Given that the optimal solution to the mapping problem is an NP-hard problem, the proposed scheme provides an efficient mapping of tasks using the particle swarm optimization algorithm. In order to be able to prevent energy consume in the infrastructure of Networks on-chip, in addition reducing latency, which is in fact one of the objectives of this study. The particle structure in this algorithm is like an array of switches in a mesh topology. The value of each particle represents a core of the communication graph. Finally, the proposed solution in the simulation environment was compared and evaluated in comparison with other common solutions. The results of different scenarios indicate that the method presented through appropriate mapping, has been able to reduce the amount of latency as well as energy consumption, which is due to the use of a solution based on particle swarm optimizing in mapping operations
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