Performance Optimization of an Electrostatically Doped Staggered Type Heterojunction Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate

Subject Areas : Journal of Optoelectronical Nanostructures

Mahdi Mohammadkhani Ghiasvand ¹ , Zahra Ahangari ² , Hamed Nematian ³

1 - Department of Electronic, Yadegar- e- Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran.
2 - Department of Electronic, Yadegar- e- Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran.
3 - Department of Electronic, Yadegar- e- Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran.

Received: 2021-12-22 Accepted : 2022-03-01 Published : 2022-01-01

Keywords: Junctionless transistor, Tunnel field effect transistor, Gate workfunction, Sensitivity, Tunneling,

Abstract :

In this paper, we demonstrate an electrostatically doped
junctionless tunnel field effect transistor which is
composed of a staggered band alignment at the
heterojunction. The proposed structure reduces the
tunneling barrier width to have a higher on-sate current
using Ge/GaAs heterojunction at the source-channel
interface. Due to the employment of electrostatically
doped strategy for creating p+-n+ tunneling junction, the
introduced device has low temperature simple fabrication
process. The device has on-state current of 1.5×10-4
(A/μm), subthreshold swing of 5.15 mV/dec and on/off
current ratio of 1.56×1010, manifesting the design of a
fast switching device. In addition, statistical analysis is
conducted to investigate the sensitivity of device
performance with respect to the variation of critical
design parameters. The results demonstrate that gate
workfunction and polarity gate bias are fundamental
design parameters and optimum value should be
determined for them to assess efficient device
performance.

References:

[1] N. Pandey, H.H Lin, A. Nandi, and Y. Taur, Modeling of short-channel effects in DG MOSFETs: Green’s function method versus scale length model, IEEE Transactions on Electron Devices, 65(8), (Jun. 2018), 3112-3119. Available: https://doi.org/10.1109/TED.2018.2845875
[2] S. Jha, and S.K. Choudhary, A comparative analysis of the short-channel effects of double-gate, tri-gate and gate-all-around MOSFETs, International Journal of Nanoparticles, 12(1-2), (Mar. 2020), 112-121. Available: https://dx.doi.org/10.1504/IJNP.2020.106002
[3] K. Pourchitsaz, M. Shayesteh, Self-heating effect modeling of a carbon nanotube-based fieldeffect transistor (CNTFET), Journal of Optoelectronical Nanostructures, 4(1), (Jan. 2019), 51-66. Available: https://dorl.net/dor/20.1001.1.24237361.2019.4.1.4.2

[4] M. Akbari Eshkalak, R. Faez, A Computational Study on the Performance of Graphene Nanoribbon Field Effect Transistor, Journal of Optoelectronical Nanostructures, 2(3), (Aug. 2017), 1-12. Available: https://dorl.net/dor/20.1001.1.24237361.2017.2.3.1.9
[5] M. Nayeri, P. keshavarzian, M. Nayeri, A Novel Design of Penternary Inverter Gate Based on Carbon Nano Tube, Journal of Optoelectronical Nanostructures, 3(1), (Jan. 2018), 15-26. Available: https://dorl.net/dor/20.1001.1.24237361.2018.3.1.2.3
[6] T. Joshi, Y. Singh, and B. Singh, Extended-source double-gate tunnel FET with improved DC and analog/RF performance, IEEE Transactions on Electron Devices, 67(4), (Mar. 2020), 1873-1879. Available: https://doi.org/10.1109/TED.2020.2973353
[7] N. Bagga, A. Kumar,and S. Dasgupta, Demonstration of a novel two source region tunnel FET, IEEE Transactions on Electron Devices, 64(12), (Oct. 2017), 5256-5262. Available: https://doi.org/10.1109/TED.2017.2759898
[8] M. Roohy, R. Hosseini, Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor, Journal of Optoelectronical Nanostructures, 4(2), (May 2019), 13-28. Available: https://dorl.net/dor/20.1001.1.24237361.2019.4.2.2.2 [9] N. Kumar, and A. Raman, Performance assessment of the charge-plasma-based cylindrical GAA vertical nanowire TFET with impact of interface trap charges, IEEE Transactions on Electron Devices, 66(10), (Aug. 2019), 4453-4460. Available: https://doi.org/10.1109/TED.2019.2935342
[10] A.K. Gupta, A. Raman, and N. Kumar, Cylindrical nanowire-TFET with Core-Shell Channel architecture: design and investigation, Silicon, 12(10), (Oct. 2020), 2329-2336. Available: https://doi.org/10.1109/TED.2019.2935342

[11] P.G. Der Agopian, J.A. Martino, A. Vandooren, R. Rooyackers, E. Simoen, A. Thean, and C. Claeys, Study of line-TFET analog performance comparing with other TFET and MOSFET architectures, Solid-State Electronics, 128, (Feb. 2017), 43-47. Available: https://doi.org/10.1016/j.sse.2016.10.021
[12] P.C. Shih, W.C. Hou, and J.Y. Li, A U-gate InGaAs/GaAsSb heterojunction TFET of tunneling normal to the gate with separate control over ON-and OFF-state current, IEEE Electron Device Letters, 38(12), (Oct 2017), 1751-1754. Available: https://doi.org/10.1109/LED.2017.2759303
[13] Y. Guan, Z. Li, W. Zhang, Y. Zhang, and F. Liang, A full-range analytical current model for heterojunction TFET with dual material gate, IEEE Transactions on Electron Devices, 65(11), (Sep. 2018), 5213-5217. Available: https://doi.org/10.1109/TED.2018.2870171
[14] A. Afzalian, E. Akhoundi, G. Gaddemane, R. Duflou, and M. Houssa, Advanced DFT–NEGF Transport Techniques for Novel 2-D Material and Device Exploration Including HfS2/WSe2 van der Waals Heterojunction TFET and WTe 2/WS 2 Metal/Semiconductor Contact, IEEE Transactions on Electron Devices, 68(11), (May 2021), 5372-5379. Available: https://doi.org/10.1109/TED.2021.3078412
[15] E.D. Kurniawan, S.Y. Yang, V. Thirunavukkarasu, and Y.C. Wu, Analysis of Ge-Si heterojunction nanowire tunnel FET: impact of tunneling window of band-to-band tunneling model, Journal of The Electrochemical Society, 164(11), (Jun 2017), E3354. Available: https://doi.org/10.1149/2.0371711jes
[16] N. Shaw, G. Sen, and B. Mukhopadhyay, An analytical approach of elimination of ambipolarity of DPDG-TFET using strained type II staggered SiGeSn heterostructure, Superlattices and Microstructures, 141, (May 2020), 106488. Available: https://doi.org/10.1016/j.spmi.2020.106488

[17] S.M. Biswal, B. Baral, D. De, and A. Sarkar, Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire (nw) Tunnel FET, Microsystem Technologies, 25(5), (May 2019),1855-1861. Available: https://doi.org/10.1007/s00542-017-3642-z
[18] P. Saha, and S.K. Sarkar, Drain current modeling of proposed dual material elliptical Gate-All-Around heterojunction TFET for enhanced device performance, Superlattices and Microstructures, 130, (Jun. 2019), 194-207. Available: https://doi.org/10.1016/j.spmi.2019.04.022 [19] Z. Ahangari, Switching Performance of Nanotube Core-Shell Heterojunction Electrically Doped Junctionless Tunnel Field Effect Transistor, Journal of Optoelectronical Nanostructures, 5(2), (May 2020) 1-12. Available: https://dorl.net/dor/20.1001.1.24237361.2020.5.2.1.8 [20] A. Riaz, M. Noor-ul-Amin, and E. Dogu, Effect of measurement error on joint monitoring of process mean and coefficient of variation, Communications in Statistics-Theory and Methods, [online] (Dec.2020),1-20. Available:https://doi.org/10.1080/03610926.2020.1867743 [21] C. Convertino, C.B Zota, H. Schmid, D. Caimi, L. Czornomaz, A.M. Ionescu, and K.E. Moselund, A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon. nature electronics, 4(2), (Feb. 2021), 162-170. Available: https://doi.org/10.1038/s41928-020-00531-3 [22] T. Vasen, P. Ramvall, A. Afzalian, G. Doornbos, M. Holland, C. Thelander, K.A. Dick, L.E. Wernersson. and M. Passlack, Vertical gate-all-around nanowire GaSb-InAs core-shell n-type tunnel FETs, Scientific reports, 9(1) (Jan. 2019),1-9. Available: https://doi.org/10.1038/s41598-018-36549-z [23] ATLAS User Manual, Santa Clara, USA: Silvaco International, 2019. Available: https://silvaco.com/