Design and Simulation of a New Capacitance Multiplier with Adaptive Current Bias and Quasi-Floating Gate Technique with Electronic Tunability and High Linearity for Biomedical Applications

Subject Areas : Electronic integrated circuits

Mohammad Aghaei Jeshvaghani ¹ , Mehdi Dolatshahi ² , Sayed Mohammad Ali Zanjani ³ , Mohammad Amin Honarvar ⁴

1 - Department of Electrical Engineering- Najafabad Branch, Islamic Azad University, Najafabad, Iran
2 - Department of Electrical Engineering- Najafabad Branch, Islamic Azad University, Najafabad, Iran
3 - Smart Microgrid Research Center- Najafabad Branch, Islamic Azad University, Najafabad, Iran
4 - Smart Microgrid Research Center- Najafabad Branch, Islamic Azad University, Najafabad, Iran

Received: 2022-07-23 Accepted : 2022-11-28 Published : 2025-02-19

Keywords: Linearity, Biomedical, capacitance multipliers, adaptive current, Electronic adjustability,

Abstract :

Employing capacitance multipliers in low-frequency integrated circuits has a significant effect on reducing the chip size area. The main idea behind the proposed circuit in this paper is to use a folded current follower (FCF) structure to effectively reduce the equivalent series resistance (ESR) in the input stage. Furthermore, using an auxiliary circuit to adapt the bias current of the transistors and applying the necessary signals by the quasi-floating gate technique (QFG), are other approaches employed to reduce the static power consumption while properly increasing the linearity of the proposed circuit, which can be considered as other benefits of the proposed approach. On the other hand, to improve the linearity, negative feedback is used and necessary voltage is applied to the gate of the transistors in the current sampler. The “K” coefficient can be adjusted by the active method. Low input resistance and high output resistance as well as the reduced occupied silicon area are achieved based on the simulation results of the proposed circuit. The simulation results in 0.18 μm technology show that, with a 0.8 V power supply and base capacitor (Cb=1 pF), for 850 nW power consumption, a capacitor equivalent to 204 pF is achieved in the proposed approach. As another example, to realize the 101 pF capacitor with the supply as mentioned above and base capacitor, the proposed multiplier requires 6.3 times less area and 23 times more bandwidth than FCF, which shows the increased accuracy of the proposed design. In the proposed circuit, in the presence of a current adaptive circuit with an input signal range of 7 nA, the output current range is obtained as 1510 nA, While the output bias current is 100nA and the harmonic distortion value is obtained as 3.6%. The proposed circuit has the highest figure of merit 42.823 MHz/μW, which shows superiority in overall performance in comparison with other reported designs.

References:

[1]   S. Alizadeh-Zanjani, A. Jannesari, P. Torkzadeh, "Design and simulation of ultra-low-power sigma-delta converter using the fully differential inverter-based amplifier for digital hearing aids application", Journal of Intelligent Procedures in Electrical Technology, vol. 13, no. 51, pp. 73–88, Dec. 2022 (in Persian) (dor: 20.1001.1.23223871.1401.13.51.5.8).

[2]   S.M.A. Zanjani, M. Dousti, M. Dolatshahi, "Inverter-based, low-power and low-voltage, new mixed-mode Gm-C filter in subthreshold CNTFET technology", IET Circuits, Devices and Systems, vol. 12, no. 6, pp. 681–688, Nov. 2018 (doi: 10.1049/iet-cds.2018.5158).

[3]   R.G. Carvajal, J. Ramirez-Angulo, A.J. Lopez-Martin, A. Torralba, J.A.G. Galan, A. Carlosena, F.M. Chavero, "The flipped voltage follower: A useful cell for low-voltage low-power circuit design", IEEE Trans. on Circuits and Systems, vol. 52, no. 7, pp. 1276–1291, July 2005 (doi: 10.1109/TCSI.2005.851387).

[4]   E. Alaybeyoglu, "Implementation of capacitor multiplier with cell-based variable transconductance amplifier", IET Circuits, Devices and Systems, vol. 13, no. 3, pp. 267–272, May. 2019 (doi: 10.1049/iet-cds.2018.5217).

[5]   F. Khateb, T. Kulej, H. Veldandi, W. Jaikla, "Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits", AEU-International Journal of Electronics and Communications, vol. 100, pp. 32–38, Feb. 2019 (doi: 10.1016/j.aeue.2018.12.023).

[6]   I. Padilla-Cantoya, "Capacitor multiplier with wide dynamic range and large multiplication factor for filter applications", IEEE Trans. on Circuits and Systems, vol. 60, no. 3, pp. 152–156, Mar. 2013 (doi: 10.1109/‌‌TCSI‌‌I.2013.2240814).

[7]   E. Alaybeyoglu, H. Kuntman, "Capacitor multiplier with high multiplication factor for integrated low pass filter of biomedical applications using DTMOS technique", AEU-International Journal of Electronics and Communications, vol. 107, pp. 291–297, June. 2019 (doi: 10.1016/j.aeue.2019.06.001).

[8]   S. Bano, G.B. Narejo, S.M.U. Ali, "Nanopower sub-threshold biquadratic cells and its application to portable ECG system", AEU-International Journal of Electronics and Communications, vol. 107, pp. 57–69, May 2019 (doi: 10.1016/j.aeue.2019.05.001).

[9]   C.Y. Sun, S.Y. Lee, “A fifth-order butterworth OTA-C LPF with multiple-output differential-input OTA for ECG applications", IEEE Trans. on Circuits and Systems, vol. 65, no. 4, pp. 421–425, April. 2018 (doi: 10.1109/T‌‌CS‌‌II.2017.2695366).

[10] C. Sawigun, S. Thanapitak, "A 0.9-nW, 101-Hz, and 46.3-μVrms IRN low-pass filter for ECG acquisition using FVF biquads", IEEE Trans. on Very Large Scale Integration Systems, vol. 26, no. 11, pp. 2290–2298, July. 2018 (doi: 10.1109/TVLSI.2018.2863706).

[11] V.S. Rajan, K.H. Kishore, R. Sanjay, B. Venkataramani, "A cross-coupled symmetric floating impedance scaler with enhanced bandwidth and accuracy", AEU-International Journal of Electronics and Commun‌‌ications, vol. 122, p. 153242, May. 2020 (doi: 10.1016/j.aeue.2020.153242).

[12] S. Solís-Bustos, J. Silva-Martínez, F. Maloberti, E. Sánchez-Sinencio, "A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications", IEEE Trans. on Circuits and Systems, vol. 47, no. 12, pp. 1391–1398, Dec. 2000 (doi: 10.1109/82.899631).

[13] M.A. Jeshvaghani, M. Dolatshahi, "Design of a low-power universal Gm-C filter in sub-threshold region", Journal of Intelligent Procedures in Electrical Technology, vol. 4, no. 15, pp. 3-10, June 2013 (in Persian) (dor: 20.100- 1.1.23223871.1392.4.15.1.9).

[14] V. Stornelli, L. Safari, G. Barile, G. Ferri, "A new extremely low power temperature insensitive electronically tunable VCII-based grounded capacitance multiplier", IEEE Trans. on Circuits and Systems, vol. 68, no. 1, pp. 72–76, June 2021 (doi: 10.1109/TCSII.2020.3005524).

[15] M.A. Al-Absi, M.T. Abuelma’atti, "A novel tunable grounded positive and negative impedance multiplier", IEEE Trans. on Circuits and Systems, vol. 66, no. 6, pp. 924–927, June 2019 (doi: 10.1109/TCSII.20‌‌18.2874511).

[16] M.A. Al-Absi, "Realization of a large values floating and tunable active inductor", IEEE Access, vol. 7, pp. 42609–42613, 2019 (doi: 10.1109/ACCESS.2019.2907639).

[17] I. Padilla-Cantoya, "Low-power high parallel load resistance current-mode grounded and floating capacitor multiplier", IEEE Trans. on Circuits and Systems, vol. 60, no. 1, pp. 16–20, Jan. 2013 (doi: 10.1109/TCSII‌‌.20‌‌12.2234923).

[18] G. Bonteanu, "A review of capacitance multiplication techniques", Proceeding of the IEEE/ECAI, no. 3, pp. 1–4, Iasi, Romania, June 2019 (doi: 10.1109/ECAI.2018.8678969).

[19] G.A. Rincon-Mora, "Active capacitor multiplier in Miller-compensated circuits", IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 26–32, Jan. 2000 (doi: 10.1109/4.818917).

[20] V.S. Rajan, R. Sanjay, S. Kumaravel, B. Venkataramani, "Area and power efficient flipped voltage follower based symmetrical floating impedance scaler with improved accuracy for fully differential filters", AEU-International Journal of Electronics and Communications, vol. 106, pp. 116–125, April 2019 (doi: 10.101‌‌6/j.ae‌‌ue.2019.04.025).

[21] S. Pourashraf, J. Ramírez-Angulo, J.M.H. Montero, R. González-Carvajal, A.J. Lopez-Martin, "±0.25-V class-AB CMOS capacitance multiplier and precision rectifiers", IEEE Trans. on Very Large Scale Integration System, vol. 27, no. 4, pp. 830–842, Nov. 2019 (doi: 10.1109/TVLSI.2018.2881249).

[22] I. Padilla-Cantoya P.M. Furth, "Enhanced grounded capacitor multiplier and Its floating implementation for analog filters", IEEE Trans. on Circuits and Systems, vol. 62, no. 10, pp. 962–966, Oct. 2015 (doi: 10.1109/T‌‌CSI‌‌I.2015.2435751).

[23] J.A. Ruiz, A.J. Lopez-Martin, J. Ramirez-Angulo, "Three novel improved CMOS C-multipliers", Internat‌‌ional Journal of Circuit Theory and Applications, vol. 40, no. 6, pp. 607-616, June 2012 (doi: 10.1002/cta.745).

[24] I. Myderrizi A. Zeki, "Electronically tunable DXCCII-based grounded capacitance multiplier", AEU-International Journal of Electronics and Communications, vol. 68, no. 9, pp. 899–906, April 2014 (doi: 10.1016/j.aeue.2014.04.013).

[25] I. Padilla-Cantoya, L. Rizo-Dominguez, J.E. Molinar-Solis, E.G. Turitsyna, S. Webb, “Capacitance multiplier with large multiplication factor, high accuracy, and low power and silicon area for floating applications,” IEICE Electronics Express, vol. 15, no. 3, Article Number: 20171191, Jan. 2018 (doi: 10.1587/elex.15.20‌‌171‌‌191).

[26] R. Sotner, J. Jerabek, L. Polak, J. Petrzela, "Capacitance multiplier using small values of multiplication factors for adjustability extension and parasitic resistance cancellation technique", IEEE Access, vol. 8, pp. 144382–144392, July 2020 (doi: 10.1109/ACCESS.2020.3014388).

[27] W. Germanovix, E. Bonizzoni, F. Maloberti, "Capacitance super multiplier for sub-hertz low-pass integrated filters", IEEE Trans. on Circuits and Systems, vol. 65, no. 3, pp. 301–305, March 2018 (doi: 10.1109/TCSII.2‌‌017.2691010).

[28] S. Banagozar, M. Yargholi, "Ultra-low power two-stage class-AB recycling double folded cascode OTA", AEU-International Journal of Electronics and Communications, vol. 110, Article Number: 152848, July 2019 (doi: 10.1016/j.aeue.2019.152848).

[29] M.P. Garde, A. Lopez-Martin, J.M. Algueta, R.G. Carvajal, J. Ramirez-Angulo, "Class AB amplifier with enhanced slew rate and GBW", International Journal of Circuit Theory and Applications, vol. 47, no. 8, pp. 1199–1210, April. 2019 (doi: 10.1002/cta.2650).

[30] S. Mehdipourm, M. Habibi, "A review of methods of reducing power on neural recording amplifiers", Journal of Intelligent Procedures in Electrical Technology, vol. 7, no. 27, pp. 55–64, Nov. 2015 (in Persian) (dor: 20.1001.1.2322‌‌3871‌‌.1395.7.27.5.8).

[31] A. Yesil, E. Yuce, S. Minaei, "Grounded capacitance multipliers based on active elements", AEU-International Journal of Electronics and Communications, vol. 79, pp. 243–249, June 2017 (doi: 10.1016/j.a‌‌eue.2017.06.006).