Design and simulation of a new sample and hold circuit with a resulation of 12-bit and a sampling rate of 1 GS/s using a dual sampling technique.

Subject Areas : Renewable energy

Najmeh Chamanpira ¹ , Seyed Mohammad Ali Zanjani ² , Mehdi Dolatshahi ³

1 - Graduate Student - Faculty of Electrical Engineering, Najaf Abad Unit, Islamic Azad University, Najaf Abad, Iran
2 - دانشکده مهندسی برق، واحد نجف‌آباد، دانشگاه آزاد اسلامی، نجف‌آباد، ایران
3 - Assistant Professor/Najafabad Branch, Islamic Azad University

Received: 2017-09-20 Accepted : 2018-04-08 Published : 2018-08-06

Keywords: Sample and hold, dual sampling, bit resolution, sampling rate,

Abstract :

In this paper, a new sample and hold circuit (S & H) with a 12 bit resolution and sampling rate of 1 GS/s is proposed using dual sampling technique. The dual sampling technique allows the circuit to always operate in higher speed and sampling rates. Furthermore, Transmission gates (TGs) are used to reduce the errors caused by nonlinear input switches because TGs have a more linear resistance in comparison with complementary- metal-oxide-semiconductor (CMOS) conventional switches. The proposed S & H circuit is simulated in the HSPICE using 180 nm CMOS and 45 nm CMOS technologies. Simulation results in both technologies with 1.8 V power supply and have power consumption of 8mW and 300 μW, respectively. Moreover, simulation results show a 12 bit resolution in both technologies, for 50.29 MHz and 43.45 MHz input frequency, for 180 nm and 45 nm respectively while the sampling frequency in both technologies is equal to 1 GHz.

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