Design of a Two-Stage Operational Amplifier Using Artificial Neural Network

Subject Areas : Renewable energy

Alireza Pourkhalili ¹ , Sayed Mohammad Ali Zanjani ²

1 - Department of Electrical Engineering- Najafabad Branch, Islamic Azad University, Najafabad, Iran
2 - Smart Microgrid Research Center- Najafabad Branch, Islamic Azad University, Najafabad, Iran

Received: 2022-07-01 Accepted : 2022-10-31 Published : 2024-08-22

Keywords: Artificial Neural Network, Operational Amplifier, Analog design optimization, Electrical design automation, Trade-off, performance modelling,

Abstract :

Design of complex analog integrated circuits requires the appropriate choice of various design parameters such as MOSFET’s aspect ratio, compensation capacitance and load capacitance in a way that improves user’s desired parameters like gain, bandwidth, power dissipation and phase margin. Considering previous works, in this paper, a two-stage miller compensated operational amplifier with PMOS input pair is designed using artificial neural network. The inputs of the neural network are design parameters including DC gain, bandwidth, power dissipation and phase margin and in its output, the sizing of transistors and the amounts of reference current supply, compensation capacitance and load capacitance are acquired. In this design method, a sampling method based on parallel HSPICE simulations is employed for data acquisition from the 15-dimensional design space which results in simplicity and automation of the dataset collecting procedure and reduces the total sampling time and then this data is used for training the neural network model. In the next stage, a range sampling method is applied for making new designs from the trained model which has facilitated the design procedure and made the user-desired tradeoffs between different performance parameters of the operational amplifier possible. Moreover, if the amplifier performance figure of merit (FOM) is defined as the result of the multiplication of unity gain bandwidth and load capacitance divided by power consumption, the comparison between obtained designs of this paper’s proposed method and the results of some other methods applied for designing operational amplifiers with relatively similar topologies in previous works, indicates that this parameter has increased by 154% at the minimum.

References:

[1] B.J. Hosticka, W. Brockherde, D. Hammerschmidt, R. Kokozinski, “Low-voltage CMOS analog circuits”, IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 42, no. 11, pp. 864-872, Nov. 1995 (doi: 10.1109/81.477197).

[2] S.P. Mohanty, E. Kougianos, “Biosensors: A tutorial review”, IEEE Potentials, vol. 25, no. 2, pp. 35-40, March/April 2006 (doi: 10.1109/MP.2006.1649009).

[3] B. Rostami, F. Shanehsazzadeh, M. Fardmanesh, “Fast fourier transform based NDT approach for depth detection of hidden defects using HTS rf-SQUID”, IEEE Trans. on Applied Superconductivity, vol. 28, no. 7, pp. 1-6, Oct. 2018 (doi: 10.1109/TASC.2018.2841927).

[4] S.M.A. Zanjani, M. Aalipour, M. Parvizi, “Design of a low power temperature sensor based on sub-threshold performance of carbon nanotube transistors with an inaccuracy of 1.5ºC for the range of -30 to 125ºC”, Journal of Intelligent Procedures in Electrical Technology, vol. 13, no. 50, pp. 115-127, Sept. 2022 (in Persian) (dor: 20.1001.1.23223871.1401.13.50.7.8).

[5] S. Alizadeh-Zanjani, A. Jannesari, P. Torkzadeh, “Design and simulation of ultra-low-power sigma-delta converter using the fully differential inverter-based amplifier for digital hearing aids application”, Journal of Intelligent Procedures in Electrical Technology, vol. 13, no. 51, pp. 73–88, Dec. 2022 (in Persian) (dor: 20.10­01.1.2­3223871.1401.13.51.5.8).

[6] P. Agrawal, H.F. Abutarboush, T. Ganesh, A.W. Mohamed, “Metaheuristic algorithms on feature selection: A survey of one decade of research (2009-2019)”, IEEE Access, vol. 9, pp. 26766-26791, Feb. 2021 (doi: 10.1109/ACCESS.2021.3056407).

[7] R.A. Rutenbar, “Simulated annealing algorithms: An overview”, IEEE Circuits and Devices Magazine, vol. 5, no. 1, pp. 19-26, Jan. 1989 (doi: 10.1109/101.17235).

[8] S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi, “Optimization by simulated annealing”, Science, vol. 220, no. 4598, pp. 671–680, May 1983 (doi: 10.1126/science.220.4598.671).

[9] E.M. Abdelkader, A. Al-Sakkaf, N. Elshaboury, G. Alfalah, “Hybrid grey wolf optimization-based aussian process regression model for simulating deterioration behavior of highway tunnel components”, Processes, vol. 10, no. 1, Article Number: 36, Dec. 2021 (doi: 10.3390/pr10010036).

[10] M. Barari, H.R. Karimi, F. Razaghian, “Analog circuit design optimization based on evolutionary algorithms”, Mathematical Problems in Engineering, vol. 2014, pp. 1–12, April 2014 (doi: 10.1155/2014/593684).

[11] Y. Jiang, J. Ju, X. Zhang, B. Yang, “Automated analog circuit design using Genetic Algorithms”, Proceeding of the IEEE/ICASID, pp. 223-228, Hong Kong, Aug. 2009 (doi: 10.1109/icasid.2009.5276912).

[12] J.B. Grimbleby, "Automatic analogue circuit synthesis using genetic algorithms", IEE Proceedings- Circuits, Devices and Systems, vol. 147, no. 6, pp. 319-323, Jan. 2001 (doi: 10.1049/ip-cds:20000770).

[13] B. Liu, F.V. Fernandez, G.G.E. Gielen, "Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 6, pp. 793–805, June 2011 (doi: 10.110­9/tc­ad.2011.2106850).

[14] H. Yuan, J. He, "Evolutionary design of operational amplifier using variable-length differential evolution algorithm", Proceeding of the IEEE/ICCASM, pp. 610-614, Taiyuan, China, Oct. 2010 (doi: 10.1109/­icca­sm.­2010.5620307).

[15] K. Kaur, Y. Kumar, “Swarm intelligence and its applications towards various computing: A systematic review”, Proceeding of the IEEE/ICIEM, pp. 57-62, London, UK, June 2020 (doi: 10.1109/ICIEM­487­62.­202­0.9160177).

[16] R.A. Vural, T. Yildirim, “Analog circuit sizing via swarm intelligence”, AEU- International Journal of Electronics and Communications, vol. 66, no. 9, pp. 732–740, Sept. 2012 (doi: 10.1016/j.aeue.2012.01.003).

[17] B. Bachir, A. Ali, M. Abdellah, "Multiobjective optimization of an operational amplifier by the ant colony optimisation algorithm", Electrical and Electronic Engineering, vol. 2, no. 4, pp. 230–235, Aug. 2012 (doi: 10.5923/j.eee.20120204.09).

[18] O. Bouattane, B. Benhala, "GA and ACO techniques for the analog circuits design optimization", Journal of Theoretical and Applied Information Technology, vol. 64, pp. 413-419, 2014.

[19] B. Benhala, A. Ahaitouf, A. Mechaqrane, B. Benlahbib, F. Abdi, E.H. Abarkan, M. Fakhfakh, “Sizing of current conveyors by means of an ant colony optimization technique”, Proceeding of the IEEE/ICMCS, pp. 1-6, Ouarzazate, Morocco, April 2011 (doi: 10.1109/ICMCS.2011.5945669).

[20] J. Dean, "A golden decade of deep learning: Computing systems & applications", Daedalus, vol. 151, no. 2, pp. 58–74, May 2022 (doi: 10.1162/daed_a_01900).

[21] Z. Zhao, L. Zhang, “Efficient performance modeling for automated CMOS analog circuit synthesis”, IEEE Trans. on Very Large-Scale Integration (VLSI) Systems, vol. 29, no. 11, pp. 1824-1837, Nov. 2021 (doi: 10.11­09/TVLSI.2021.3107404).

[22] H. Yang, C. Meng, C. Wang, “Data-driven feature extraction for analog circuit fault diagnosis using 1-D convolutional neural network”, IEEE Access, vol. 8, pp. 18305-18315, Jan. 2020 (doi: 10.1109/ACCE­SS.20­20.2968744).

[23] M. Hayati, A. Rezaei, M. Seifi, "CNT-MOSFET modeling based on artificial neural network: Application to simulation of nanoscale circuits", Solid-State Electronics, vol. 54, no. 1, pp. 52–57, Jan. 2010 (doi: 10.1016/j.sse.2009.09.027).

[24] E. Afacan, N. Lourenço, R. Martins, G. Dündar, "Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test", Integration, vol. 77, pp. 113–130, March 2021 (doi: 10.1016/j.vlsi.2020.11.006).

[25] S. Du, H. Liu, H. Yin, F. Yu, J. Li, "A local surrogate-based parallel optimization for analog circuits", AEU- International Journal of Electronics and Communications, vol. 134, Article Number: 153667, May 2021 (doi: 10.1016/j.aeue.2021.153667).

[26] C.C. Chang, J. Pan, T. Zhang, Z. Xie, J. Hu, W. Qi, C.W. Lin, R. Liang, J. Mitra, E. Fallon, Y. Chen, “Automatic routability predictor development using neural architecture search”, Proceeding of the IEEE/ACM-ICCAD, pp. 1-9, Munich, Germany, Nov. 2021 (doi: 10.1109/ICCAD51958.2021.9643483).

[27] N. Takai, M. Fukuda, "Prediction of element values of OPAmp for required specifications utilizing deep learning", Proceeding of the IEEE/ISESD, Yogyakarta, Indonesia, Oct. 2017 (doi: 10.1109/isesd.­2017.8253353).

[28] S. Zhang, W. Lyu, F. Yang, C. Yan, D. Zhou, X. Zeng, “Bayesian optimization approach for analog circuit synthesis using neural network”, Proceeding of the IEEE/DATE, pp. 1463-1468, Florence, Italy, March 2019 (doi: 10.23919/DATE.2019.8714788).

[29] B. He, S. Zhang, F. Yang, C. Yan, D. Zhou, X. Zeng, “An efficient aussian optimization approach for analog circuit synthesis via sparse aussian process modeling”, Proceeding of the IEEE/DATE, pp. 67-72, Grenoble, France, March 2020 (doi: 10.23919/DATE48585.2020.9116366).

[30] B. Rajabi, F. Razaghian, "Analog circuit complementary optimization based on evolutionary algorithms and artificial neural network", Signal Processing and Renewable Energy, vol. 2, no. 1, pp. 15-26, March 2018 (dor: 20.1001.1.25887327.2018.2.1.3.1).

[31] Y. Li, Y. Lin, M. Madhusudan, A. Sharma, W. Xu, S.S. Sapatnekar, R. Harjani, J. Hu, "A customized graph neural network model for guiding analog IC placement", Proceeding of the IEEE/ACM, pp. 1-9, San Diego, CA, USA, Nov. 2020 (doi: 10.1145/3400302.3415624).

[32] Y. Li, Y. Wang, Y. Li, R. Zhou, Z. Lin, “An artificial neural network assisted optimization system for analog design space exploration”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10, pp. 2640-2653, Oct. 2020 (doi: 10.1109/TCAD.2019.2961322).

[33] A. Budak, M. Gandara, W. Shi, D. Pan, N. Sun, B. Liu, “An efficient analog circuit sizing method based on machine learning assisted global optimization”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1209-1201, May 2022 (doi: 10.1109/TCAD.2021.3081405).

[34] N. Kahraman, T. Yildirim, “Technology independent circuit sizing for fundamental analog circuits using artificial neural networks”, Proceeding of the IEEE/RME, pp. 1-4, June/April 2008 (doi: 10.1109/RME.2008.4595710).

[35] J.P.S. Rosa, D.J.D. Guerra, N.C.G. Horta, R.M.F. Martins, N.C.C. Lourenço, "Using artificial neural networks for analog integrated circuit design automation", Springer Cham, Switzerland Springer, Jan. 2020 (ISBNN: 978-3-030-35742-9).

[36] N. Lourenço, E. Afacan, R. Martins, F. Passos, A. Canelas, R. Póvoa, N. Horta, G. Dundar, “Using polynomial regression and artificial neural networks for reusable analog IC sizing”, Proceeding of the SMACD, pp. 13-16, Lausanne, Switzerland, July 2019 (doi: 10.1109/SMACD.2019.8795282).

[37] V.K. Devabhaktuni, M.C.E. Yagoub, Y. Fang, J. Xu, Q.J. Zhang, "Neural networks for microwave modeling: Model development issues and nonlinear modeling techniques", International Journal of RF and Microwave Computer-Aided Engineering, vol. 11, no. 1, pp. 4–21, Jan. 2001 (doi: 10.1002/1099-047x(200101)).

[38] T. Dhaene, J. Ureel, N. Fache, D.D. Zutter, “Adaptive frequency sampling algorithm for fast and accurate S-parameter modeling of general planar structures”, Proceedings of the IEEE/MWSYM, vol. 3, pp. 1427-1430 Orlando, FL, USA, May 1995 (doi: 10.1109/MWSYM.1995.406240).

[39] P.B.L. Meijer, "Fast and smooth highly nonlinear multidimensional table models for device modeling", IEEE Trans. on Circuits and Systems, vol. 37, no. 3, pp. 335–346, Mar. 1990 (doi: 10.1109/31.52727).

[40] J. Mitchell, W. McDaniel, “Adaptive sampling technique”, IEEE Trans. on Automatic Control, vol. 14, no. 2, pp. 200-201, April 1969 (doi: 10.1109/TAC.1969.1099144).

[41] U. Beyer and F. Śmieja, “Data exploration with reflective adaptive models,” Computational Statistics & Data Analysis, vol. 22, no. 2, pp. 193–211, Jul. 1996, (doi: 10.1016/0167-9473(95)00048-8).

[42] V.K. Devabhaktuni, Q.J. Zhang, “Neural network training-driven adaptive sampling algorithm for microwave modeling”, Proceeding of the EUMA, pp. 1-4, Paris, France, Oct 2000 (doi: 10.1109/EUMA.2000.338591).

[43] Z. Wang, X. Luo, Z. Gong, "Application of deep Learning in analog circuit sizing", Proceedings of the CSAI, pp. 571–575, Shenzhen China, Dec.2018 (doi: 10.1145/3297156.3297160).

[44] E. Siggiridou, D. Kugiumtzis, “Dimension reduction of polynomial regression models for the estimation of granger causality in high-dimensional time series”, IEEE Trans. on Signal Processing, vol. 69, pp. 5638-5650, Oct. 2021 (doi: 10.1109/TSP.2021.3114997).

[45] G.T. Toussaint, “Polynomial representation of classifiers with independent discrete-valued features”, IEEE Trans. on Computers, vol. C-21, no. 2, pp. 205-208, Feb. 1972 (doi: 10.1109/TC.1972.5008928).

[46] Y.Y. Hsin, T.S. Dai, Y.W. Ti, M.C. Huang, T.H. Chiang, L.C. Liu, “Feature engineering and resampling strategies for fund transfer fraud with limited transaction data and a time-inhomogeneous modi operandi”, IEEE Access, vol. 10, pp. 86101-86116, Aug. 2022 (doi: 10.1109/ACCESS.2022.3199425).

[47] G.B. Huang, “Learning capability and storage capacity of two-hidden-layer feedforward networks”, IEEE Trans. on Neural Networks, vol. 14, no. 2, pp. 274-281, March 2003 (doi: 10.1109/TNN.2003.809401).

[48] J. Ke, X. Liu, “Empirical analysis of optimal hidden neurons in neural network modeling for stock prediction”, Proceeding of the IEEE/PACIIA, pp. 828-832, Wuhan, China, Dec. 2008 (doi: 10.1109/PACIIA.2008.363).

[49] S. Trenn, “Multilayer perceptrons: Approximation order and necessary number of hidden units”, IEEE Trans. on Neural Networks, vol. 19, no. 5, pp. 836-844, May 2008 (doi: 10.1109/TNN.2007.912306).

[50] W. Qu, S. Singh, Y. Lee, Y.S. Son, G.H. Cho, “Design-oriented analysis for miller compensation and its application to multistage amplifier design”, IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 517-527, Feb. 2017 (doi: 10.1109/JSSC.2016.2619677).

[51] D. Marano, A.D. Grasso, G. Palumbo, S. Pennisi, “Optimized active single-miller capacitor compensation with inner half-feedforward stage for very high-load three-stage OTAs”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 63, no. 9, pp. 1349-1359, Sept. 2016 (doi: 10.1109/TCSI.2016.2573920).

[52] S. K. Rajput, B.K. Hemant, “Two-stage high gain low power OpAmp with current buffer compensation”, Proceeding of the IEEE/GHTCE, pp. 121-124, Shenzhen, China, Nov. 2013 (doi: 10.1109/GH­TCE.2­01­3.6­76­7255).

[53] S.M.H. Largani, S. Shahsavari, S. Biabanifard, A. Jalali, "A new frequency compensation technique for three stages OTA by differential feedback path: SMC, frequency compensation, differential feedback path", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 28, no. 4, pp. 381–388, July 2015 (doi: 10.1002/jnm.2013).

[54] S. M. Anisheh, C. Dadkhah, “A two-stage method for optimizing the parameters of CMOS operational amplifiers based on evolutionary algorithm”, The CSI Journal on Computer Science and Engineering, vol. 14, no. 2, pp. 1-10, Winter 2017.

[55] B.P. De, K.B. Maji, R. Kar, D. Mandal, S.P. Ghoshal, “Application of improved PSO for optimal design of CMOS two-stage Op-amp using nulling resistor compensation circuit”, Proceeding of the IEEE/DevIC), pp. 110-115, Kalyani, India, March 2017 (doi: 10.1109/DEVIC.2017.8073917).

[56] B.P. De, K.B. Maji, R. Kar, D. Mandal, S.P. Ghoshal, "Design of optimal CMOS analog amplifier circuits using a hybrid evolutionary optimization technique", Journal of Circuits, Systems and Computers, vol. 27, no. 02, Article Number: 1850029, Sept. 2017 (doi: 10.1142/s0218126618500299).

[57] M.A.M. Majeed, P.S. Rao, "Optimal design of CMOS amplifier circuits using whale optimization algorithm", Communications in Computer and Information Science, pp. 590–605, Oct. 2018 (doi: 10.1007/978-981-13-2372-0_53).

[58] H. Gupta, B. Ghosh, "Analog circuits design using ant colony optimization", International Journal of Electronics Communication and Computer Technology, vol. 2, pp.  9-21, May 2012.

[59] S. Asaithambi, M. Rajappa, L. Ravi, "Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm", Journal of Intelligent and Fuzzy Systems, vol. 36, no. 5, pp. 4235–4245, May 2019 (doi: 10.3233/jifs-169981).

[60] S.M.A. Zanjani, M. Parvizi, “Design and simulation of a bulk driven operational trans-conductance amplifier based on CNTFET technology”, Journal of Intelligent Procedures in Electrical Technology, vol. 12, no. 45, pp. 63-74, June 2021 (in Persian) (dor: 20.1001.1.23223871.1400.12.1.5.1).