An Optimized Four-Bit Multiplier using Transmission Gate Diffusion Input Technique

Subject Areas : Electronic Engineering

Javad Hassanli ¹ , nabiallah شیری ² , Farshad Pesaran ³

1 - Student
2 - Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran
3 - Islamic Azad University, Shiraz Branch

Received: 2023-12-10 Accepted : 2024-01-22 Published : 2024-10-08

Keywords: Multiplier, transmition gate (TG), gate diffusion input (GDI), optimization,

Abstract :

Arithmatic units in high-speed cores usually contain digital multipliers, and their optimization has a significant impact on the speed of arithmetic and computer systems. Different design techniques have been presented in the research. In this study, a 4-bit multiplier is optimized using transmission gate (TG) and gate diffusion input (GDI) techniques. The GDI technique reduces the number of transistors, propagation delay, power consumption, and chip area. Also, using the TG technique compensates for the swing error at the output of the multiplier. The optimized multiplier is evaluated by 90 nm technology. The results show that the multiplier has 6.09 µW power consumption, 6.146 ns delay, and 200 × 200 µm² area. Also, the value of PDP (Power Delay Product) of the circuit is equal to 37.45×10^-15. The optimized multiplier applies to efficient digital signal processors (DSPs) where high performance is required.

References:

[1] M. Rafiee, F. Pesaran, A. Sadeghi, and N. Shiri, “An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications,” Microelectronics Journal, vol. 118, p. 105287, Dec. 2021, https://doi.org/10.1016/j.mejo.2021.105287.
[2] A. Sadeghi, N. Shiri, M. Rafiee, and M. Tahghigh, "An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending," Frontiers of Information Technology & Electronic Engineering, vol. 23, no. 6, pp. 950-965, 2022/06/01 2022, http://dx.doi.org/10.1631/FITEE.2100432.
[3] M. Fadaei, "Designing ALU using GDI method," International Journal of Reconfigurable and Embedded Systems, vol. 8, no. 3, p. 151, 2019, http://doi.org/10.11591/ijres.v8.i3.pp151-161.
[4] A. Morgenshtein, A. Fish, and I. A. Wagner, "Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization," in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 26-29 May 2002 2002, vol. 1, pp. I-I, https://doi.org/10.1109/ISCAS.2002.1009881.
[5] A. P. Chandrakasan, W. J. Bowhill, and F. Fox, "Design of high-performance microprocessor circuits, " Wiley-IEEE press, 2000, https://www.wiley.com/en-us/Design+of+High-Performance+Microprocessor+Circuits-p-9780780360013.
[6] K. Bernstein et al., "High speed CMOS design styles, " Springer Science & Business Media, 1998, https://link.springer.com/book/10.1007/978-1-4615-5573-5.
[7] A. Garg and G. Joshi, "Gate diffusion input based 4‐bit Vedic multiplier design," IET Circuits, Devices & Systems, vol. 12, no. 6, pp. 764-770, 2018, https://doi.org/10.1049/iet-cds.2017.0454.
[8] S. Sharma and V. Sharda, "Design and analysis of 8-bit Vedic multiplier in 90nm technology using GDI technique," Int. J. Eng. Technol, vol. 7, no. 3.12, p. 759, 2018, http://dx.doi.org/10.14419/ijet.v7i3.12.16496.
[9] G. Nayan, "A Comparative Analysis of 8-bit Novel Adder Architecture Design using Traditional CMOS and m-GDI technique," in 2019 International Conference on Communication and Electronics Systems (ICCES), 17-19 July 2019 2019, pp. 128-135, https://doi.org/10.1109/ICCES45898.2019.9002573.
[10] G. Nayan, R. K. Prasad, P. K. YG, and D. M. Kurian, "A Review on Modified Gate Diffusion Input Logic: An Approach for Area and Power Efficient Digital System Design," in Proceedings of the Second International Conference on Emerging Trends in Science & Technologies For Engineering Systems (ICETSE-2019), 2019, http://dx.doi.org/10.2139/ssrn.3507293.
[11] D. E. Nikonov and I. A. Young, "Overview of beyond-CMOS devices and a uniform methodology for their benchmarking," Proceedings of the IEEE, vol. 101, no. 12, pp. 2498-2533, 2013, http://dx.doi.org/10.1109/JPROC.2013.2252317.
[12] A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, "Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design," Integration, vol. 47, no. 1, pp. 62-70, 2014, http://dx.doi.org/10.1016/j.vlsi.2013.04.002.
[13] A. Morgenshtein, A. Fish, and I. A. Wagner, "Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits," IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no. 5, pp. 566-581, 2002, http://dx.doi.org/10.1109/TVLSI.2002.801578.
[14] M. Dai, Z. Song, C.-H. Lin, Y. Dong, T. Wu, and J. Chu, "Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction," Communications Materials, vol. 3, no. 1, p. 41, 2022, http://dx.doi.org/10.1038/s43246-022-00261-3.
[15] S. Dayanand, K. Varshitha, T. Rohini, Y. J. M. Shirur, and J. R. Munavalli, "Low Power High Speed Vedic Techniques in Recent VLSI Design–A Survey," Perspectives in Communication, Embedded-systems and Signal-processing-PiCES, vol. 4, no. 6, pp. 147-156, 2020, https://doi.org/10.5281/zenodo.4247825.
[16] X. Li, W. Cheng, T. Zhang, J. Xie, F. Ren, and B. Yang, "Power efficient high performance packet I/O," in Proceedings of the 47th International Conference on Parallel Processing, 2018, pp. 1-10, http://dx.doi.org/10.1145/3225058.3225129.
[17] S. Vaidya and D. Dandekar, "Delay-power performance comparison of multipliers in VLSI circuit design," International Journal of Computer Networks & Communications (IJCNC), vol. 2, no. 4, pp. 47-56, 2010, http://dx.doi.org/10.5121/ijcnc.2010.2405.
[18] S. Nair and A. Saraf, "A review paper on comparison of multipliers based on performance parameters," International Journal of Computer Applications, vol. 5, no. 4, pp. 6-9, 2014, https://api.semanticscholar.org/CorpusID:9515631.
[19] S. J. Lee and S. H. Ruslan, "A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method," International Journal of Integrated Engineering, vol. 10, no. 3, 2018, http://dx.doi.org/10.30880/ijie.2018.10.03.004.
[20] M. Bansal and J. Singh, "Comparative analysis of 4-bit CMOS vedic multiplier and GDI vedic multiplier using 18nm FinFET technology," in 2020 International Conference on Smart Electronics and Communication (ICOSEC), 2020: IEEE, pp. 1328-1332, http://dx.doi.org/10.1109/ICOSEC49089.2020.9215317.
[21] K. Gurumurthy and M. Prahalad, "Fast and power efficient 16× 16 Array of Array multiplier using Vedic Multiplication," in 2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference, 2010: IEEE, pp. 1-4, http://dx.doi.org/10.1109/IMPACT.2010.5699463.
[22] C. K. Tung, S. H. Shieh, and C. H. Cheng, "Low‐power high‐speed full adder for portable electronic applications," Electronics Letters, vol. 49, no. 17, pp. 1063-1064, 2013, http://dx.doi.org/10.1049/el.2013.0893.
[23] S. Ziabakhsh and M. Zoghi, "Design of a low-power high-speed t-flip-flop using the gate-diffusion input technique," in Proc. 17th Telecommunications forum TELFOR, 2009, pp. 1470-1473, http://dx.doi.org/10.1109/IranianCEE.2014.6999508.
[24] N. Tiwari, R. Sharma, and R. Parihar, "Implementation of area and energy efficient Full adder cell," in International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), 2014: IEEE, pp. 1-5, http://dx.doi.org/10.1109/ICRAIE.2014.6909248.