An Optimized Four-Bit Multiplier using Transmission Gate Diffusion Input Technique

Subject Areas : Electronic Engineering

Javad Hassanli ¹ , nabiallah شیری ² , Farshad Pesaran ³

1 - Student
2 - Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran
3 - Islamic Azad University, Shiraz Branch

Received: 2023-12-10 Accepted : 2024-05-26 Published : 2024-09-12

Keywords: Multiplier, transmition gate (TG), gate diffusion input (GDI), optimization,

Abstract :

Arithmatic units in high-speed cores usually contain digital multipliers, and their optimization has a significant impact on the speed of arithmetic and computer systems. Different design techniques have been presented in the research. In this study, a 4-bit multiplier is optimized using transmission gate (TG) and gate diffusion input (GDI) techniques. The GDI technique reduces the number of transistors, propagation delay, power consumption, and chip area. Also, using the TG technique compensates for the swing error at the output of the multiplier. The optimized multiplier is evaluated by 90 nm technology. The results show that the multiplier has 6.09 µW power consumption, 6.146 ns delay, and 200 × 200 µm² area. Also, the value of PDP (Power Delay Product) of the circuit is equal to 37.45×10^-15. The optimized multiplier applies to efficient digital signal processors (DSPs) where high performance is required.

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