Improving The Design of Adder Using FinFET Transistor

Subject Areas : Information Technology in Engineering Design (ITED) Journal

Ali Asghar Taj Abadi ^{1 *} , Mahdiyeh Eslami ² , mehdi jafari ³

1 -
2 - Electrical Eng. Dep, Kerman Branch, Islamic Azad University, Kerman, Iran
3 - Department of electronic Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran

Received: 2025-01-10 Accepted : 2025-02-15 Published : 2025-06-21

Keywords: Full Adder, FinFET, Reverse Saturation Current, Average power consumption, Circuit Delay,

Abstract :

One of the most commonly used blocks in computer calculations is adders, which serve as a major part of the processor to compute register addresses and other arithmetic operations. The speed of the adder determines how fast the processor will execute, and designers are currently more focused on high speed and low power consumption. Nowadays, with the reduction in the scale of electronic components in manufacturing technology, in order to increase the density of transistors on a chip, issues such as short-channel effects, gate tunneling, and so on arise, which reduce the performance of the component. To reduce these effects, one of the structures that has received significant attention in manufacturing technologies is the FinFET, which effectively reduces these effects and increases the switching speed of the device by providing better electrostatic control over the channel. In this research, a new adder based on FinFET technology has been designed. This full adder is designed using two half adders and 10 transistors. The new full adder has been simulated in the HSPICE software. The simulation results show a significant reduction in power consumption and Power Delay Product.

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