Modelling of Drain Current of MOSFET Transistor in Terms of Gate Oxide Thickness

Subject Areas : Majlesi Journal of Telecommunication Devices

Masoud Pourgholam ¹ , Bahram Azizollah Ganji ²

1 - Babol Noshirvani University of Technology
2 -

Received: 2016-01-27 Accepted : 2016-04-26 Published : 2016-05-01

Keywords:

References:

[1] C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, California, Berkeley: Prentice Hall, 2009.

[2] M. Zabeli, N. Caka, M. Limani and Q. Kabashi, “The impact of MOSFET’s physical parameters on its threshold voltage, ” in 6th WSEAS Int. Conf. Microelectronics, Nanoelectronics, Optoelectronics, Istanbul, Turkey, 2007.

[3] M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara and S. Miyazaki, “Limit of Gate Oxide Thickness Scaling in MOSFETs due to Apparent Threshold Voltage Fluctuation Induced by Tunnel Leakage Current, ” IEEE Trans. on Electron Device, vol. 48, no. 2, pp. 259-264, 2001.

[4] I. Safayat-Al, “Effects of gate insulator thickness and diameter over on/off current ratio in ballistic CNTFETs, ” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 2, no. 11, pp. 5424-5429, 2013.

[5] N. Gupta, “Threshold voltage modelling and gate oxide thickness effect on polycrystalline silicon thin-film transistors, ” IOP Publishing, Physica Scripta, vol. 76, pp. 628-633, 2007.

[6] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, Wiley-Interscience, 2006.