Highly Energy-Efficient and Small-Area Single-Bit Approximate GDI-Based Subtractor for Dividers' Implementation

Subject Areas : Electronic Engineering

Fatemeh Pooladi ¹ , Farshad Pesaran ² , nabiallah شیری ³

1 - Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran
2 - Islamic Azad University, Shiraz Branch
3 - استاد دانشکاه آزاد شیراز-صدرا

Received: 2023-11-01 Accepted : 2023-12-22 Published : 2024-02-08

Keywords: Subtractor, divider, approximate calculations, carbon nanotube.,

Abstract :

In digital circuits that have a high number of transistors, energy dissipation is still a challenge. New techniques like approximate computing are somehow helpful for challenge solving. Therefore, three new single-bit subtractors are presented based on the approximate computing and gate diffusion input (GDI) technique. Compared to the literature, proposed circuits 1-3 with different truth tables have 10, 8, and 6 transistors, respectively, which causes a significant reduction in power consumption. The simulation results based on the carbon nanotube field effect transistor (CNTFET) technology with a channel length of 32 nm confirmed the superiority of the circuits. The proposed circuit 3 with no inverter has the best circuitry performance. However, due to the presence of 4 errors in this circuit, its error rate is higher compared to other circuits. Examining the effects of changes in the voltage source, the fan-outs, and the process-voltage-temperature (PVT) variations showed a superior energy performance of the proposed circuit 3. Also, by embedding the proposed circuits in the 8-bit divider structure, the superiority of the proposed circuit 3 in terms of various figures of merits was observable by at least 50%.

References:

[1] W. Liu, F. Lombardi and M. Shulte, "A Retrospective and Prospective View of Approximate Computing [Point of View}," in Proceedings of the IEEE, vol. 108, no. 3, pp. 394-399, March 2020, doi: 10.1109/JPROC.2020.2975695.
[2] H. Jiang, F. J. H. Santiago, H. Mo, L. Liu and J. Han, "Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications," in Proceedings of the IEEE, vol. 108, no. 12, pp. 2108-2135, 2020, doi: 10.1109/JPROC.2020.3006451.
[3] A. Sadeghi, R. Ghasemi, H. Ghasemian and N. Shiri, "High Efficient GDI-CNTFET-Based Approximate Full Adder for Next-Generation of Computer Architectures," in IEEE Embedded Systems Letters,vol. 15, no. 1,pp: 33-36. Jul. 2022, doi: 10.1109/LES.2022.3192530.
[4] M. Rafiee, Y. Sadeghi, N. Shiri, A. Sadeghi, , "An approximate CNTFET 4:2 compressor based on gate
diffusion input and dynamic threshold". Electron. Lett.vol. no. 17, pp.650-652. Aug 2021. doi: 10.1049/ell2.12221.
[5] Gorantla, A., Deepa, P. "Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications". J Electron Test 35 vol. no. 6 , pp:901–907 (2019). doi.org/10.1007/s10836-019-05837-5.
[6] L. Chen, J. Han, W. Liu and F. Lombardi, "On the Design of Approximate Restoring Dividers for Error-Tolerant Applications," in IEEE Transactions on Computers, vol. 65, no. 8, pp. 2522-2533, 1 Aug. 2016, doi: 10.1109/TC.2015.2494005.
[7] Bahrami F, Shiri N, Pesaran F. "A New Approximate Sum of Absolute Differences Unit for Bioimages Processing". IEEE Embedded Systems Letters. vol. Feb 2023. doi: 10.1109/LES.2023.3245020.
[8] O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, "Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1352-1361, April 2017, doi: 10.1109/TVLSI.2016.2643003.
[9] A. G. M. Strollo, E. Napoli, D. De Caro, N. Petra and G. D. Meo, "Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3021-3034, Sept. 2020, doi: 10.1109/TCSI.2020.2988353.
[10] R. Ferreira, M. Leme, M. Corrêa, L. Agostini, C. Diniz and B. Zatt, "Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators," in IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol.pp. 426-429, Nov 272019 doi: 10.1109/ICECS46596. 8964783.
[11] L. Chen, J. Han, W. Liu and F. Lombardi, "On the Design of Approximate Restoring Dividers for Error-Tolerant Applications," in IEEE Transactions on Computers, vol. 65, no. 8, pp. 2522-2533, 1 Aug. 2016, doi: 10.1109/TC.2015.2494005.
[12] K. Manikantta Reddy, M. H. Vasantha, Y. B. Nithin Kumar and D. Dwivedi, "Design of Approximate Dividers for Error Tolerant Applications," IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), vol. pp. 496-499, Aug 2018 doi: 10.1109/MWSCAS.2018.8623909.
[13] R. Ferreira, M. Leme, M. Corrêa, L. Agostini, C. Diniz and B. Zatt, "Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators," IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. pp. 426-429 Nov 27.2019, doi: 10.1109/ICECS46596.2019.8964783.
[14] K. V. Krishnan, A. Satish, P. r. Krishnan,"Design of energy efficient approximate subtractors and restoring dividers for error tolerant applications",Microelectronics Journal,Vol.pp:1;131:105668,Jan 2023 doi.org/10.1016/j.mejo.2022.105668.
[15] M. Mirzaei and S. Mohammadi, "Low-power and variation-aware approximate arithmetic units for image processing applications," AEU Int. J. Electron. Commun., vol.pp: 1;138:153825.Aug 2021. doi.org/10.1016/j.aeue.
[16] M. Mirzaei and S. Mohammadi,"Process variation-aware approximate full adders for imprecision-tolerant applications," Comput. Electr. Eng. vol. 1;87:106761. Oct 2020.doi.org/1016/j.compelceng.
[17] A. Sadeghi, N. Shiri, and M. Rafiee, “High-efficient, ultra-low-power and high-speed 4:2 compressor with a new full adder cell for bioelectronics applications,” Circuits Syst. Signal Process., vol. 39, pp. 6247–6275, Jun. 2020. doi.org/10.1007/s00034-020-01459-x.
[18] F. Pooladi, F. Pesaran, N. Shiri," Efficient GDI-based approximate subtractors for change detection in bio-image processing applications". Microelectronics Journal. Vol. 135. 105757.2023.
doi.org/10.1016/j.mejo.2023.105757
[19] F. Sabetzadeh, M. H. Moaiyeri and M. Ahmadinejad, "A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4200-4208, 2019. doi.org/10.1109/tcsl.