Using Cross-Coupled model to design negative capacitor in CMOS technology

Subject Areas : Electronic Engineering

Mohsen Katebi Jahromi ¹ ( دانشگاه آزاد اسلامی واحد صفاشهر )
mohsen safavi ² ( Department of Electrical Engineering, Safashahr Branch, Islamic Azad University, Safashahr, Iran )

Received: 2023-10-08 Accepted : 2023-10-10 Published : 2023-10-13

Keywords: negative capacitor, Cross-Coupled, CMOS technology, power consumption,

Abstract :

In this paper, the Cross-Coupled model is used to design the negative capacitor in CMOS technology, and then the negative capacitor and its application in various circuits are investigated and studied. The investigation and study of the negative capacitor and its application in various circuits have been discussed In the following article, the proposed circuit was drawn in the Cadence software using 180 nm technology with a capacitor of 5pF, the dimension of the chip, considering the capacitor of 5 pF, is equal to 152/80 ×40/61 µm. The dimension of the non-capacitor chip is 32 ×61.40 µm. In the second step, the proposed circuit was simulated in ADS software and its frequency response and power consumption were checked. The simulation results show that with a load capacitor of 5 pF in the range frequency of 500 MHz, the negative capacitor is produced in the range of -1.5 to -20 pF, that is the power consumption is about 3.5 mW with a 1.8 V power supply. The wide frequency range of the negative capacitor, relatively low power consumption and good quality factor are the advantages of this design.

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