A Quaternary Representative for Serial Transceiver Using Pulse Slope Encoding

Subject Areas : International Journal of Smart Electrical Engineering

Mosslem Amiri ¹ (Automation and Instrumentation Expert, Automation and Instrumentation Department, HGS Ltd. Shiraz, Iran)

Received: 2021-09-22 Accepted : 2021-10-24 Published : 2022-03-01

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8                                     International Journal of Smart Electrical Engineering, Vol. , No. ,                    ISSN: 2251-9246        

EISSN: 2345-6221

 

pp :

 

A Quaternary Representative for Serial Transceiver Using Pulse Slope Encoding

Mosslem Amiri 1*

 

1Automation and Instrumentation Department, HGS Ltd., Shiraz, Iran, [e-mail]

      

Abstract

In this paper, a new scheme for serial communication is proposed. In this method, in addition to the pulse states (high and low), either of negative slope or positive slope of the pulse (saw-tooth waveform) is employed as a representative for another digit. Using pulse slope as a representative for a separate digit will result in sending two-bit-digits using a single pulse, which doubles the transfer rate. The proposed scheme can be used in both synchronized and asynchronized communications and can improve communication speed. Through simulating the proposed scheme, it turned out that this method, because of its proper immunity to noise, can be used as a peripheral interface alongside in-chip communication. The main idea in the raised discussion is to obtain four different geometric pulse shapes acting as four different numbers in the quaternary numeric system, in which it can be serialized/desrialized as easy as pulse states. This proposed method and the suggested system for serialization and deserialization of data can be an adequate alternative in high-speed communication approaches.

Keywords: binary codes, bitrate, communication system signaling, data communication, digital systems, frequency, logic circuits, noise

Article history:

© 2020 IAUCTB-IJSEE Science. All rights reserved

 

1.       Introduction

 

Advances in IC fabrication technology, coupled with the aggressive circuit design, have led to an exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer-to-peripheral connections, local area networks, memory buses, and multiprocessor interconnection networks. Designers are concerned that these links will soon reach the fundamental limits of electrical signalling [1]. Trying to meet the bandwidth demands of the modern systems results in costly wide buses and high pin-count chips and modules [2]. Overcoming this limitation requires more sophisticated signalling methods which can transfer more data without increment of data rate or growth of buses and I/O pins [1], [2], [3]. Otherwise, because signalling rates do not scale with improving semiconductor technology, many high-performance electrical signalling microprocessors operate their external buses at a small fraction of their internal clock rate [2].

To summarize, in nowadays digital systems, data transfer speed is more limited by PCB, cable geometry and skin-effect loss, and not by VLSI and IC fabrication technology [4], [5], [6], [7].

Using various representatives for transmission of data, aside from digital states (high and low states of pulses) can be a beneficial approach for achieving higher transfer rates without increasing frequency. In this paper, an innovative quaternary scheme is proposed which can be a novel alternative to the binary system for data communication within in-chip-communication as well as peripheral interfaces communication.

In the next section, physical limitations for high-frequency data communication will be described briefly. And in the third section, a suggested block diagram for the proposed system, as a PISO/serializer/encoder system in the transmitter and a SIPO/deserializer/decoder system in the receiver is depicted in a simplex data transceiver system. In the fourth section, the possibility of extending data bits and the procedure of data bits’ extension are studied. The fifth section is devoted to simulating and investigating the practical aspects of the proposed scheme of communication. In the last section, a comparison between the proposed quaternary scheme and the conventional binary scheme will be made and the discussion will be concluded.

2.       Limits on Signaling Rate

The data rate of a signaling system is limited by both the electronics used to generate and receive signal, and also the medium which the signal is transmitted over. Electronics limits the signaling rate due to rise-time, aperture time, and timing uncertainty [8].

Fig. 1. Limitations on the timing of the transmitted signal.

The time for a bit cell (tbit) must be made long enough for the signal to slew from one logic level to another (tr), and for the receiver to sample this signal while stable (ta), and to tolerate jitter between the signal and the sampling clock (2tu). Fig. 1 shows limitations on the timing of the transmitted signal.

 

All three of these factors are related to the basic time constant of semiconductor technology (τn). The time for a minimum-sized nFET to discharge the gate of an equalized nFET [8], [9]. This time constant is given approximately by following equation: [9] 

With careful design, an incident-wave signalling system can achieve a bit cell width of 15-30τn (150-300ps in 0.35µm technology) [2]. The signalling rate scales linearly with the basic time constant of the technology (τn), independent of the wire length. As gate lengths continue to shrink according to the SIA roadmap the speed of signalling systems can improve at the same rate [10]. In spite of that, while the speed of the transmitter and receiver improve as the gate length of semiconductor technology shrinks, the bandwidth of the wire used to connect the transmitter to the receiver remains constant [8]. Frequency-dependent attenuation due to the skin-effect resistance of the wire is the major factor that limits wire bandwidth. Impedance discontinuities are not a limiting factor. In a well-designed system, the transmission path from the transmitter to the receiver has a constant impedance with no appreciable discontinuities to attenuate the signal and cause inter-symbol interference. With some insulating materials, dielectric absorption also causes a frequency-dependent attenuation; However, this effect can be mitigated by using a low-loss dielectric. The skin-effect attenuation in dB at frequency “f” of a wire with length “d” is given by following equation: [2]

Where “A1” is the attenuation of a 1m wire at frequency “f1”. For example, the attenuation of a 100Ω, 24AWG twisted pair is 0.45dB/m at 1GHz (A1 = 0.45dB/m, f1 = 1GHz). At 10GHz, a 1m wire has an attenuation of 1.4dB/m and a 10m wire has an attenuation of 14dB. Attenuation is also proportional to the inverse of the wire radius, so one can get lower attenuation by using fatter wires. Because this attenuation is frequency-dependent, it causes inter-symbol interference and signal energy reduction. At an attenuation of 6dB, the unattenuated low-frequency components of the signal completely swamp the high-frequency components. Equalizing the signal, by pre-emphasizing the high-frequency components of the signal before transmission, eliminates the inter-symbol interference caused by the frequency-dependent nature of the attenuation [2]. With perfect equalization, the amount of attenuation that can be tolerated is limited by the noise floor. A receiver limited by Johnson noise in a 50Ω environment at 300°K has a noise floor in dBV of following equation: [2]

One may be able to build receivers with a better noise temperature than 300°K, with ideal coding, one can recover over one bit per symbol with a 20dB SNR, and one could operate with higher transmit power levels. The distance limits assume that we can build an equalized channel to correct frequency-dependent attenuation. This ranges from 73dB at 1Gb/s to 53dB at 100Gb/s. To date, we have implemented Gb/s-rate equalizers that correct for up to 10dB of frequency-dependent attenuation. Closing the gap between 10dB and 70dB requires solving many engineering problems to build more precise equalizers. Also, to achieve this limit, we must cancel many sources of receiver offset and interference to build a high-speed receiver that is limited by thermal noise. The fact that most radio receivers operate at the thermal limit, however, suggests that this goal is feasible [2].

So far, limiting factors of growth in the frequency within digital systems have been declared. In the following sections, a quaternary representation for data communication is introduced, which can improve the transfer rate without requiring frequency growth.

3.       Block Diagram of the Proposed System

In this section, tow general procedures for encoding and decoding data using the proposed scheme will be illustrated, important waveforms will be depicted and the process of the system will be described.

3.1. Overall Block Diagram for PISO/Serializer/Encoder

Fig. 2. Overall block diagram for the PISO/serializer/encoder of the proposed communication scheme.

Fig. 2 illustrates an overall block diagram for the PISO/serializer/encoder procedure of the proposed communication scheme, which is applicable as the transmitter.

 

 

In the fig. 2 block diagram, a generated clock is divided by 2 and afterward, positive slopes and negative slopes are produced from that using two integrators, for the representation of “10(b)” and “11(b)” respectively. Likewise, for the representation of “00(b)” and “01(b)”, outputs of “Low State” and “High State” blocks are predicted respectively. When parallel data (B0…B7) are ready and a serialization start pulse (VS) is provided, serialization starts. on the falling edge of VS, delay blocks will be triggered and in turn, tow pulses with high state duration of 6.1*Ton and 8*Ton will be produced to enable counter block and latch block, respectively. Where Ton is half the period of the clock pulse (VC). The output of latch write/clear delay block (VP) is provided after 2*Ton, to improvise latched data for analogue multiplexer before serialization starts. The output of the counter delay block (VP2) should be at high state after 3.9*Ton. To accomplish needed delay pulses (VP and VP2), each delay block has comprised two serial Monostable multi-vibrators, in which the first one lags state change of the second Monostable.

At the rising edge of the VP, the input parallel data will be latched on the output of the 8-bits latch block. Afterward, data will be inserted to the analogue multiplexer address, through a Boolean circuit, which controls the transition of applied bits. Table I shows the truth table of the employed Boolean Circuit.

 

The truth table of the employed Boolean circuit in Fig. 2

Counter

Data

Out2

Out1

0

0

B7

B6

B5

B4

B3

B2

B1

B0

B1

B0

0

1

B7

B6

B5

B4

B3

B2

B1

B0

B3

B2

1

0

B7

B6

B5

B4

B3

B2

B1

B0

B5

B4

1

1

B7

B6

B5

B4

B3

B2

B1

B0

B7

B6

 

As it is seen in table I, each pair of B0…B7 data bits are inserted as the multiplexer address, by every increment in the counter. Hence, every two bits of the input data is encoded as one of the four pre-defined representations sequentially. And the output will be a four-packet-stream, in which every packet is an individual representative for a half nibbles of input byte. Fig. 3 shows the waveforms and signals of fig. 2 PISO/serializer/encoder system.

 

Fig. 3. The waveforms and signals of figure 2 PISO/serializer/encoder.

It should be mentioned that in this paper a general scheme of encoding is introduced. Synchronization and clock recovery discussions, using negative voltages and bipolar encoding, identifications and header packets needed in the networking, and error control techniques are very important issues which are deliberately neglected in this paper to prohibit the expansion of discussion. Generally, the designed scheme is depicted here as a monopole (without negative state) signaling, without the error correction method. Also, the clock recovery method is assumed as either synchronization using direct transmission of the clock between sent data frames, or pre-defined fixed clock speed, and the related details will not be depicted and discussed.

3.2. Overall Block Diagram for SIPO/Deserializer/Decoder

Fig. 4 illustrates an overall block diagram for the SIPO/deserializer/decoder procedure of the proposed communication scheme, which is applicable as the receiver.

 

Fig. 4. Overall block diagram for SIPO/deserializer/decoder of proposed communication scheme.

 

In the designed block diagram, “Differentiator”, “Amp” and “Clipper” blocks are used to differentiate the input serial stream. After differentiating and amplifying the input stream, the clipper block rejects unwanted impulses. The gain of these three blocks are determined so the output voltage (VDIFF2) fit in the range of 0.6…1.4 V for the positive slope and the range of -0.6…-1.4 V for the negative slope. Afterward, tow window detectors are implemented which detect the mentioned ranges of voltage and provide the logic high state in their output. Examinations indicated that using a primitive window detector causes symbol error in the output, therefor implemented window detector is modified and enhanced, which will be described elaborately in section V. “Clipper” block used in fig. 4, which its input is Vi, is a logic clipper Schmitt-trigger to provide a high state logic in the presence of the high state in the input stream. The outputs of tow window detectors and the Schmitt trigger block is inserted to a Boolean circuit to provide needed tow-bits of data, according to the current state of the input stream. Table 2 shows the truth table of the employed Boolean circuit.

 

The truth table of the employed Boolean circuit in Fig. 4

VSch	VW1	VW2	VB1	VB0
1	X	X	0	1
X	1	X	1	0
X	X	1	1	1

 

As it is depicted in fig. 4, “Clock Recovery” and “x2 Frequency Multiplier” blocks produce a proper clock pulse (VC) and insert it to a five-bits shift register. During the period that there is no input to SIPO system, data input of the shift register is low and all the outputs of the shift register are held low until “start bit detector” senses a start bit, and inserts detected high state into the shift register. When the start bit is detected, at the first falling edge of the clock pulse, Q0 changes to the high state. Sequentially, the rising edge of Q0 clears the output latches. Consequently, the next pulses of the clock shift the high state to Q1 through Q4. Each of Q1…Q4 outputs situates a pair of output latches in the write activated condition. Consequently, data bits corresponding to the serial input stream (VB0 and VB1) will be latched in the output of activated latches respectively. For the four packets of input serial stream, corresponding data bits are produced and latched as described. At the eighth pulse of VC after detection of the start bit, the high state is inserted to Q5 and all eight bits of parallel output data (B0…B7) are prepared. Q5 is used as a data ready signal to declare that output data is ready to be harvested. Fig. 5 shows the waveforms and signals of fig. 4 SIPO/deserializer/decoder system.

 

Fig. 5. Waveform and signals of figure 4 deserializer/decoder.

4.       Extension of Data Bits in the Proposed Scheme

So far, the proposed communication scheme has been studied with eight bits of data. Nowadays, most of the communication systems use 16, 32 or 64 bits of data, and it is a necessity for a communication scheme to have the ability to profit extension of communicating data bits. The proposed scheme can be extended in data bits by changing the capacity of blocks, which will be described flowingly. Certainly, the extension of data bits outgrows the hardware in any communication system. Extension of data bits in the fig. 2 PISO block diagram will be accomplished with extending the input latch, and up-counter size, as well as expanding the employed Boolean circuit. Conversely, the analogue multiplexer remains the same. Analog multiplexer and other blocks of PISO system do not need any changes for extension of data bits.

For extending the SIPO block diagram illustrated in fig. 4, shift register and data latches should be extended to reach the capacity needed for more data bits, and other blocks will remain intact without changes.

To summarize, for an n-bits communication scheme a q-bits up-counter and an n-bits input latch are needed in PISO system. Which “q” is given by equation (4).

Whereas, the SIPO system needs a t-bits shift register and an n-bits output latch. Where “t” is given by equation (5).

Fig. 6 shows the important waveforms and signals of the proposed scheme with 16 data bits.

 

Fig. 6. The important waveforms and signals of the proposed scheme with 16-bits of data bits.

5.       Simulation of the Proposed Scheme in Simulink

The proposed design for communication has been evaluated using MATLAB Simulink, and results are presented in this section.

Fig. 7 depicts the evaluated design. Since used blocks in this simulation are known standard blocks, except when necessary, details of modelled sketch and implemented blocks are not discussed, and the discussion will be focused on the results.

 

Fig. 7. The modeled sketch of the proposed communication system for evaluating in MATLAB Simulink

 

Fig. 7 shows an eight-bits communication system which serializes and deserializes three bytes of data using the proposed communication scheme, with VK=5MHz and VC=10MHz. In the PISO system, input 8-bits data are randomly produced using eight “Bernoulli Binary Generator” blocks. four “Discrete integrator” blocks are implemented for shaping positive and negative slopes. VP and VP2 delays are provided by four “Monostable” blocks. Tow “Uniform Random Number” blocks are used to simulate channel noise, and a “Gain” block is manipulated as transmission channel attenuator.

In the SIPO system, the serial stream is differentiated using a “Differentiator Filter” block, and “Saturation” blocks are used as Schmitt-trigger clippers. It should be mentioned, as it was cleared before, the focus of this paper is to propose an innovative quaternary scheme of communication, therefore clock recovery system is not simulated, and needed clock in modelled SIPO system is provided directly using “Pulse Generator” block.

Fig. 8 shows the generated V0, V1, V2, and V3 waveforms.

 

 

Fig. 8. Generated V0, V1, V2, and V3 waveforms.

 

Fig. 9 shows clock pulses (VC and VK), serialization start (VS), delay pulses (VP1 and VP2), Boolean circuit outputs (A0 and A1), and PISO system output (VOUT).

 

Fig. 9. Clock pulses (VC and VK), serialization start (VS), delay pulses (VP1 and VP2), Boolean circuit outputs (A0 and A1), and PISO output (VOUT) waveforms.

Fig. 10 shows the output of the PISO system, modelled noise of transmission line, the output signal plus noise (Vi), which is input to the SIPO system, differentiation of Vi (VDiff), the output of clipper block (VDiff2), the outputs of window detectors, and the output of Schmitt-trigger clipper (VSch).

 

Fig. 10. PISO output, modeled noise of transmission line, the output signal plus noise (Vi), differentiation of Vi (VDiff), the output of clipper block (VDiff2), outputs of window detectors, and output of Schmitt-trigger clipper (VSch) waveforms.

As it is seen in fig. 10, the outputs of the differentiator blocks are pulsating rapidly due to unwanted noises which are combined with the main signal. This issue causes wrong quantization and symbol error. By careful observation of VDIFF2 it is clear that regardless of pulsations due to fine slope changes, the mean value of differentiator blocks output, as well as the definite integration of VDiff2 are distinguishably greater in the presence of slope, which could be detected properly by optimization of window detector. examinations showed that the definite integration of VDIIF2 signal in tVc periods can provide a distinctive characteristic for proper noise isolation of SIPO system. Therefore, Window detector blocks are optimized as shown in fig. 11 to accomplish the previously discussed task.

 

Fig. 11. Optimized window detector blocks.

Fig. 12 depicts Vi, VDIFF2 and the output of the definite integrator blocks, which can well help to understand the function of optimized window detectors.

 

Fig. 12. Vi, VDIFF2 and the output of the definite integrator block waveforms.

It should be mentioned that the comparison blocks (≥2 block) in the fig. 11 diagram are used for providing logic high state for their following Boolean circuit and output latch blocks before the appearance of the clock edge on the CLK pin of latch blocks. It is well clear in fig. 12 waveform that anytime output of the definite integral block rises over “2”, the input stream definitely contains the corresponding positive or negative slopes. External reset of integral output is used on both edges of VC to reset the output to the initial condition of zero before the start of the next definite integration procedure.

Fig. 13 shows the output signals of the blocks in the SIPO system.

 

Fig. 13. Employed Boolean circuit outputs (VB1 and VB2), Schmitt-trigger clipper output, shift register outputs (Q0… Q5), and ADC output waveforms.

In fig. 13, VB1 and VB2 are outputs of the employed Boolean circuit, Q0… Q4 are shift register outputs. Also Q0 is the first bit of the shift register outputs, which is used for clearing output latches. Q5 is the sixth bit of the shift register outputs, which indicates that output parallel data is prepared. And the ADC graph is the output of an ADC block, which converts the SIPO system output to analogue, for better depiction of the 8-bits digital output.

6.       Comparison and Conclusion

Presented study and results of simulations show that the proposed scheme of communication has a reliable practical application for utilization in electronics digital. The presented quaternary scheme compared to the same design using the binary system provides higher transfer rate. Although certainly utilizing the binary system in communications provide better results in quantization and also decreases the noise effects on the symbol error without forcing extra procedures for noise cancellation. However, simulations show that the proposed scheme can obtain proper noise isolation using an adequate SIPO system design. And also it should be cleared that through assessments of the proposed system, it turned out that the main evident disadvantage of the proposed system is the complexity of hardware, compared to the binary system scheme of communication.

In the end, it should be declared that this discussion is raised to outline a feasible approach for overcoming transfer rate growth limitation in the modern electronic communication, and the author believes that the concept of the proposed method might potentially become expanded and developed soon. More improvements can be made through exploring the new schemes for communicating using octal (base 8) or even hexadecimal (base 16) representative schemes and the results indeed can ripen and enrich the raised discussion.

 

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