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عنوان URL للمقالة


رقم المقالة : JOPN-2211-1274 (R2) زيارة : 99 الصفحة: 13 - 31

10.30495/jopn.2023.31255.1274

20.1001.1.24237361.2023.8.1.2.8

نوع المخطوط: ابحاث

Controlling Ambipolar Current in a Junctionless Tunneling FET Emphasizing on Depletion Region Extension

الموضوعات : فصلنامه نانوساختارهای اپتوالکترونیکی

Morteza Rahimian 1

1 - Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran

تاريخ الإرسال : 27 الإثنين , ربيع الثاني, 1444 تاريخ التأكيد : 18 الأحد , صفر, 1445 تاريخ الإصدار : 08 الأحد , جمادى الثانية, 1444

الکلمات المفتاحية: Junctionless tunneling field effect transistors (J-TFETs), Ambipolar current, Depletion region, Tunneling barrier width, Band-toband tunneling (BTBT),

ملخص المقالة :

Abstract:
For the first time, in this research, we introduce a
junctionless tunneling FET (J-TFET) on a uniform p+
starting junctionless FET to realize appreciable immunity
against inherent high ambipolar current (Iamb). So, we
utilize two isolated gates with appropriate workfunctions
over the channel and drain regions to create P+IP+N+
charge distribution. This structure utilizes a space
between the gate-drain electrodes (SGD), to provide a
P+IP+N+ structure thanks to the effective electrons
depletion on the drain side. Increasing the SGD, further
effectively pulls up the bands near the interface between
the channel-drain regions, widens the tunneling width for
tunneling to occur, and thus in turn reduces the Iamb from
5.37×10-7 A/µm to 1.14×10-14 A/µm. Thus, we point out
that the proposed J-TFET can obtain on-current that
satisfies the expectation of logic applications with high
performance and Ioff that meets the specifications of low
power characteristics, a phenomenon that is rarely
accessible with conventional TFETs.

المصادر:


  1. Rahimian and Ali. A. Orouji. Investigation of the electrical and thermal performance of SOI MOSFETs with modified channel engineering. Mater Sci Semicond Process., 16 (5) (Oct. 2013) 1248-1256. Available: https://doi.org/10.1016/j.mssp.2012.12.001
    2.
  2. Rahimian, Ali. A. Orouji and A. Aminbeidokhti. A novel deep submicron SiGe-on-insulator (SGOI) MOSFET with modified channel band energy for electrical performance improvement. Curr. Appl Phys., 13 (4) (Jun. 2013) 779-784. Available: https://doi.org/10.1016/j.cap.2012.12.005
    3.
  3. Bahrami, M. R. Shayesteh, M. Pourahmadi, H. Safdarkhani. Improvement of the Drive Current in 5nm Bulk-FinFET Using Process and Device Simulations. J Opt Nanostructures., 5 (1) (Feb. 2020) 65-81. Available: https://dorl.net/dor/20.1001.1.24237361.2020.5.1.5.0
    4.
  4. Ionescu and H. Riel. Tunnel field-effect transistors as energy efficient electronic switches. Nature., 479 (7373) (Nov. 2011) 329-337. Available: https://doi.org/10.1038/nature10679
    5.
  5. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu. Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec. IEEE Electron Device Lett., 28 (8) (Aug. 2007) 743–745. Available: https://doi.org/10.1109/LED.2007.901273
    6.
  6. Zhang, W. Zhao and A. Seabaugh. Low-Subthreshold-Swing Tunnel Transistors. IEEE Electron Device Lett., 27 (4) (Apr. 2006) 297–300. Available: https://doi.org/10.1109/LED.2006.871855
    7.
  7. A. Eshkalak, R. Faez. A Computational Study on the Performance of Graphene Nanoribbon Field Effect Transistor. J Opt Nanostructures., 2 (3) (Aug. 2017) 1-12. Available: https://dorl.net/dor/20.1001.1.24237361.2017.2.3.1.9
    8.
  8. T. Björk, J. Knoch, H. Schmid, H. Riel, and W. Riess. Silicon nanowire tunneling field effect transistors. Appl. Phys. Lett., 92 (Apr. 2008) 193504–193506. Available: https://doi.org/10.1063/1.2928227
    9.
  9. Rahimian and M. Fathipour. Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric. Mater Sci Semicond Process., 63 (1) (Jun. 2017) 142–152. Available: https://doi.org/10.1016/j.mssp.2016.12.011
    10.
  10. Keighobadi, S. Mohammadi, M. Mohtaram. Recessed Gate Cylindrical Heterostructure TFET, a Device with Extremely Steep Subthreshold Swing. Trans. Electr. Electron. Mater., 23 (Apr. 2021) 81–87. Available: https://doi.org/10.1007/s42341-021-00321-4
    11.
  11. Musalgaonkar, Sh. Sahay, R. S. Saxena and M. J. Kumar. Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study. IEEE Trans. Electron Devices., 66 (10) (Oct. 2019) 4425–4432. Available: https://doi.org/10.1109/TED.2019.2933756
    12.
  12. Rahimian, and M. Fathipour. Asymmetric junctionless nanowire TFET with built-in n+ source pocket emphasizing on energy band modification. J. Comput. Electron., 15 (4) (Dec. 2016) 1297–1307. Available: https://doi.org/10.1007/s10825-016-0895-1
    13.
  13. Ahangari. Switching Performance of Nanotube Core-Shell Heterojunction Electrically Doped Junctionless Tunnel Field Effect Transistor. J Opt Nanostructures., 5 (2) (May. 2020) 1-12. Available: https://dorl.net/dor/20.1001.1.24237361.2020.5.2.1.8
    14.
  14. M. Ghiasvand, Z. Ahangari, H. Nematian. Performance Optimization of an Electrostatically Doped Staggered Type Heterojunction Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate. J Opt Nanostructures., 7 (1) (Jan. 2022) 19-36. Available: https://doi.org/10.30495/jopn.2022.29617.1249
    15.
  15. K. Anvarifard, Ali A. Orouji. Energy Band Adjustment in a Reliable Novel Charge Plasma SiGe Source TFET to Intensify the BTBT Rate. IEEE Trans. Electron Devices., 68 (10) (Oct. 2021) 5284–5290. Available: https://doi.org/10.1109/TED.2021.3106891
    16.
  16. Musalgaonkar, Sh. Sahay, R. S. Saxena and M. J. Kumar. A Line Tunneling Field-Effect Transistor Based on Misaligned Core–Shell Gate Architecture in Emerging Nanotube FETs. IEEE Trans. Electron Devices., 66 (6) (Jun. 2019) 2809–2816. Available: https://doi.org/10.1109/TED.2019.2910156
    17.
  17. N. Kumar, S. I. Amin, and S. Anand. Design and Performance Optimization of Novel Core–Shell Dopingless GAA-Nanotube TFET With Si0.5Ge0.5-Based Source. IEEE Trans. Electron Devices., 67 (3) (Mar. 2020) 789–795. Available: https://doi.org/10.1109/TED.2020.2965244
    18.
  18. Rahimian, and M. Fathipour. Junctionless nanowire TFET with built-in n-p-n bipolar action: physics and operational principle. J. Appl. Phys., 120 (22) (Nov. 2016) 225702. Available: https://doi.org/10.1063/1.4971345
    19.
  19. Roohy, R. Hosseini. Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor. J Opt Nanostructures., 4 (2) (May. 2019) 13-28. Available: https://dorl.net/dor/20.1001.1.24237361.2019.4.2.2.2
    20.
  20. Li, H. Liu, Sh. Wang, Sh. Cheng, T. Han, K. Yang. Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling. AIP Adv., 9 (Mar. 2019) 045109. Available: https://doi.org/10.1063/1.5087879
    21.
  21. M. Imen Abadi, S. Ali S. Ziabari. Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications. Microelectron. Eng., 162 (16) (Aug. 2016) 12-16. Available: https://doi.org/10.1016/j.mee.2016.04.016
    22.
  22. Chahardah Cherik, S. Mohammadi. Germanium‑source L‑shaped TFET with dual in‑line tunneling junction. Appl. Phys. A., 127 (Jun. 2021) 525–532. Available: https://doi.org/10.1007/s00339-021-04677-5
    23.
  23. Shekhar, A. Raman. Design and analysis of dual‑gate misalignment on the performance of dopingless tunnel field effect transistor. Appl. Phys. A, 126 (May. 2020) 441–449. Available: https://doi.org/10.1007/s00339-020-03615-1
    24.
  24. P. Goswami, B. Bhowmick, Optimization of Electrical Parameters of Pocket Doped SOI TFET with L Shaped Gate. Silicon, 12 (May. 2019) 693–700. Available: https://doi.org/10.1007/s12633-019-00169-7
    25.
  25. Sahay and M. J. Kumar, Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX. IEEE Trans. Electron Devices, 62 (11) (Nov. 2015) 3882–3886. Available: https://doi.org/10.1109/TED.2015.2478955
    26.
  26. B. Abdi and M. J. Kumar, Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain. IEEE J. Electron Devices Soc, 2 (6) (Nov. 2014) 187–190. Available: https://doi.org/10.1109/JEDS.2014.2327626
    27.
  27. Bavir, A. Abbasi, Ali. A. Orouji. Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications. J. Electron. Mater., 51 (Jan. 2022) 2083-2094. Available:
    28.
  28. https://doi.org/10.1007/s11664-022-09462-5
    29.
  29. Madadi, Ali. A. Orouji. Stacked Single-Gate Silicon on Insulator 4H-SiC Junctionless Field-Effect Transistor with a Buried P-Type 4H-SiC Layer. Phys. Status Solidi., 219 (11) (Jun. 2022) 2100504. Available: https://doi.org/10.1002/pssa.202100504
    30.
  30. Aslam, G. Korram, D. Sharma, Sh. Yadav, N. Sharma, Enhancement of the DC performance of a PNPN hetero‑dielectric BOX tunnel field‑effect transistor for low‑power applications. J. Comput. Electron, 19 (Dec. 2019) 271–276. Available: https://doi.org/10.1007/s10825-019-01427-y
    31.
  31. K. Singh, M. R. Tripathy, S. Chander, K. Baral, P. K. Singh, S. Jit, Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure. Silicon, 12 (Dec. 2019) 2345–2354. Available: https://doi.org/10.1088/1361-6641/ab542b
    32.
  32. Kumar, B. Raj, B. Raj, Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design. Silicon, 13 (Jun. 2020) 1599–1607. Available: https://doi.org/10.1007/s12633-020-00547-6
    33.
  33. Zafar, M. A. Raushan, Sh. Ahmad, M. J. Siddiqui, Reducing off-state leakage current in dopingless transistor employing dual metal drain. Semicond. Sci. Technol, 35 (1) (Dec. 2019). Available: https://doi.org/10.1088/1361-6641/ab542b
    34.
  34. Y. Chang, S. Chopra, B. Adams, J. Li, Sh. Sharma, Y. Kim, S. Moffatt, J. C.S. Woo, Improved subthreshold characteristics in tunnel field-effect transistors using shallow junction technologies. Solid State Electron, 80 (Feb. 2013) (59-62). Available: https://doi.org/10.1016/j.sse.2012.10.013
    35.
  35. Damrongplasit, S. H. Kim, and T. J. K. Liu, Study of Random Dopant Fluctuation Induced Variability in the Raised-Ge-Source TFET. IEEE Electron Device Lett, 34 (2) (Feb. 2013) 184-186. Available: https://doi.org/10.1109/LED.2012.2235404
    36.
  36. Damrongplasit, Ch. Shin, S. H. Kim, R. A. Vega and T. J. K. Liu, Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs. IEEE Trans. Electron Devices, 58 (10) (Oct. 2011) 3541–3548. Available: https://doi.org/10.1109/TED.2011.2161990
    37.
  37. Ghosh and M. W. Akram, Junctionless Tunnel Field Effect Transistor. IEEE Electron Device Lett, 34 (5) (May. 2013) 584–586. Available: https://doi.org/10.1109/LED.2013.2253752
    38.
  38. K. Asthana, B. Ghosh, Y. Goswami, and B. M. M. Tripathi, High-Speed and Low-Power Ultra deep-Submicrometer III–V Heterojunctionless Tunnel Field-Effect Transistor. IEEE Trans. Electron Devices, 61 (2) (Feb. 2014) 479–485. Available: https://doi.org/10.1109/TED.2013.2295238
    39.
  39. J. Kumar and S. Janardhanan, Doping-Less Tunnel Field Effect Transistor: Design and Investigation. IEEE Trans. Electron Devices, 60 (10) (Oct. 2013) 3285–3290. Available: https://doi.org/10.1109/TED.2013.2276888
    40.
  40. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, Nanowire transistors without junctions. Nature Nanotechnol, 5 (3) (Mar. 2010) 225–229. Available: https://doi.org/10.1038/nnano.2010.15
    41.
  41. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, Theory of the Junctionless Nanowire FET. IEEE Trans. Electron Devices, 58 (9) (Sep. 2011) 2903–2910. Available: https://doi.org/10.1109/TED.2011.2159608
    42.
  42. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, Junctionless multigate field-effect transistor. Appl. Phys. Lett. 94 (5) (Jan. 2009) 53511-53513. Available: https://doi.org/10.1063/1.3079411
    43.
  43. Bolokian, Ali. A. Orouji, A. Abbasi, M. Houshmand. Pyramid P+ area in SOI junction-less MOSFET for logic applications: DC investigation. Appl. Nanosci., (Feb. 2023). Available: https://doi.org/10.1007/s13204-023-02808-3 M. Bolokian, Ali. A. Orouji, A. Abbasi, D. Madadi.
    44.
  44. Bavir, A. Abbasi, Ali. A. Orouji. Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet. IEEE J. Electron Devices Soc., 10 (Apr. 2022) 334-340. Available: https://doi.org/10.1109/JEDS.2022.3166708
    45.
  45. Realization of Double-Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer. Phys. Status Solidi., 219 (21) (Nov. 2022) 2200214. Available: https://doi.org/10.1002/pssa.202200214
    46.
  46. Ch. Cherik, A. Abbasi, S. K. Maity, S. Mohammadi. Junctionless tunnel field-effect transistor with a modified auxiliary gate, a novel candidate for high-frequency applications. Micro and Nanostructures., 174 (Feb. 2023). Available: https://doi.org/10.1016/j.micrna.2022.207477
    47.
  47. ATLAS Device Simulation Software, Silvaco, Santa Clara, CA, USA, 2019. Available: https://silvaco.com/
    48.
  48. Hänsch, T. Vogelsang, R. Kircher, and M. Orlowski, Carrier transport near the Si/SiO2 interface of a MOSFET. Solid State Electron. 32 (10) (Oct. 1989) 839-849. Available: https://doi.org/10.1016/0038-1101(89)90060-9
    49.
  49. Xiong and J. Bokor, Sensitivity of double-gate and FinFET Devices to process variations. IEEE Trans. Electron Devices, 50 (11) (Nov. 2003) 2255–2261. Available: https://doi.org/10.1109/TED.2003.818594
    50.
  50. -P. Colinge, J. C. Alderman, W. Xiong, and C. R. Cleavelin, Quantum–mechanical effects in trigate SOI MOSFETs. IEEE Trans. Electron Devices, 53 (5) (May. 2006) 1131–1136. Available: https://doi.org/10.1109/TED.2006.871872
    51.
  51. Rahimian, Two Dimensional Analytical Modeling and Simulation for Junctionless Tunneling Field Effect Transistors, presented at the 7th Int. Conf. Electrical Engineering, Computer Science, & Information Technology, Hamedan, Iran, (2023) Feb. 5-7. Available: https://civilica.com/doc/1638014
    52.

 

 

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