Improvement of the Drive Current in 5nm Bulk-FinFET Using Process and Device Simulations
الموضوعات : فصلنامه نانوساختارهای اپتوالکترونیکی
Payman Bahrami
1
(Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran)
Mohammad Reza Shayesteh
2
(Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran)
Majid Pourahmadi
3
(Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran)
Hadi Safdarkhani
4
(Department of Electrical Engineering, Yazd University, Yazd, Iran)
الکلمات المفتاحية: Threshold Voltage, FinFET, Manufacturing Process, Drive Current, DIBL Effect,
ملخص المقالة :
Abstract: We present the optimization of the manufacturing process of the 5nm bulk-
FinFET technology by using the 3D process and device simulations. In this paper, by
simulating the manufacturing processes, we focus on optimizing the manufacturing
process to improve the drive current of the 5nm FinFET. The improvement of drive
current is one of the most important issues in the FinFETs design. We first investigate
the impact of manufacturing process parameters include gate oxide thickness, type of
the gate oxide, height of fin, and doping of the source and drain region on threshold
voltage, breakdown voltage, and drive current of the transistor. Then, by selecting the
optimal parameters of the manufacturing process, we improve the drive current of the
5nm bulk-FinFET.
[1] K. Pourchitsaz and M. R. Shayesteh, Self-heating effect modeling of a carbon nanotube-based fieldeffect transistor (CNTFET), Journal of Optoelectronical Nanostructures 4 (1) (2019, Jan.) 51-66. [2] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, T. Elewa, Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Letters 8 (9) (1987, Sep.) 410-412. [3] O. Semenov, A.Vassighi, M. Sachdev, A. Keshavarzi, CF. Hawkins, Effect of CMOS technology scaling on thermal management during burn-in, IEEE transactions on semiconductor manufacturing 16 (4) (2003, Nov.) 686-695.
[4] G. Saini, AK. Rana, Physical scaling limits of FinFET structure: A simulation study, International Journal of VLSI design & communication Systems (VLSICS) 2 (1) (2011, Mar.) 26-35. [5] M. Roohy, and R. Hosseini, Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor, Journal of Optoelectronical Nanostructures 4 (2) (2019, May.) 13-28.
[6] SP. Mohanty, Nanoelectronic mixed-signal system design, New York: McGraw-Hill Education, 2015, 78-94.
[7] W. Han, Toward Quantum FinFET, ZM. Wang, editor. Springer, 2013, 54-67.
[8] P. Mishra, A. Muttreja, N. K. Jha, FinFET circuit design, in Nanoelectronic Circuit Design, Springer, 2011, 23–54.
[9] R. Das, R. Goswami, and S. Baishya, Tri-gate heterojunction SOI Ge-FinFETs, Superlattices Microstruct 91 (2016, Mar.) 51–61.
[10] V. E. Dorgan, M.-H. Bae, and E. Pop, Mobility and saturation velocity in graphene on SiO2, Applied Physics Letters 97 (8) (2010, Aug.), 82112.
[11] A. T. M. Fairus, V. K. Arora, Quantum engineering of nanoelectronic devices: the role of quantum confinement on mobility degradation, Microelectronics Journal, 32 (8) (2001, Aug.) 679–686. [12] B. Azizollah-Ganji, and M. Gholipour, Effects of the channel length on the nanoscale field effect diode performance, Journal of Optoelectronical Nanostructures 3 (2) (2018, Jun.) 29-40.
[13] V. K. Arora, Theory of scattering-limited and ballistic mobility and saturation velocity in low-dimensional nanostructures, Current Nanoscience 5 (2), (2009, May.) 227–231.
[14] V. Kilchytska, S. Makovejev, S. Barraud, T. Poiroux, J.-P. Raskin, D. Flandre, Trigate nanowire MOSFETs analog figures of merit, Solid-State Electronics, 112, (2015, Oct.) 78–84. [15] N. Collaert, A. De Keersgieter, K. G Anil, and et al., Performance improvement of tall triple gate devices with strained SiN layers, IEEE electron device letters 26 (11) (2005, Oct.) 820-822.
[16] J. Kedzierski, High-performance symmetric-gate and CMOS compatible Vt asymmetric-gate FinFET devices, in IEDM Tech. Dig., (2001) 437-440. [17] T. Kanemura, T. Izumida, N. Aoki, M. Kondo, and et al., Improvement of drive current in bulk-FinFET using full 3D process/device simulations, In IEEE International Conference on Simulation of Semiconductor Processes and Devices (2006, Sep.) 131-134. [18] A. Sachid, C. Min-Cheng, and H. Chenming , FinFET With High-ê Spacers for Improved Drive Current. IEEE electron device letters 37(7) (2016, May.) 835-838.
[19] X. Wang, A. R. Brown, B. Cheng, and A. Asenov, Statistical variability and reliability in nanoscale FinFETs, in Electron Devices Meeting (IEDM), 2011 IEEE International, (2011, Dec.) 4–5.
[20] I. Ferain, C. A. Colinge, and J.-P. Colinge, Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors, Nature 479 (7373), (2011, Nov.) 310.
[21] C. H. Wang, P.-F. Zhang, Three-dimensional DIBL for shallow-trench isolated MOSFET’s, IEEE Transactions on Electron Devices 46 (1) (1999, Jan.) 139–144.
[22] Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power, by H. I. Hanafi, R. H. Dennard, W. E. Haensch. (2006, Aug.) Google Patents [Online]. Available:https://patents.google.com/patent/US7089515B2/en
[23] T. Skotnicki, Heading for decananometer CMOS-Is navigation among icebergs still a viable strategy?, in Solid-State Device Research IEEE (2000, Sep.) 19–33.
[24] S. Sengupta, S. Pandit, Study of LER/LWR induced V T variability of an EنDC n-channel MOS transistor, in Devices for Integrated Circuit (DevIC) (2017, Mar.) 685–689.
[25] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging, in Electron Devices Meeting (2007, Dec.) 247–250.
[26] C. H. Jan, U. Bhattacharya, R. Brain, S.J. Choi, G. Curello, G. Gupta, W. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications, in Electron Devices Meeting (IEDM) (2012, Dec.) 1–3.
[27] M. Radosavljevic, G. Dewey, J. M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, Non-planar, multi-gate InGaAs quantum well field effect transistors with high-k gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications, inElectron Devices Meeting (IEDM) (2010, Dec.) 1–6.
