طراحی و شبیه‌سازی مدارهای جمع‌کننده کم‌مصرف با استفاده از گیت MGDI در فناوری QCA
محورهای موضوعی : مهندسی برق و کامپیوتر
حمیدرضا صدر ارحامی
1
,
سیدمحمدعلی زنجانی
2
,
مهدی دولتشاهی
3
,
بهرنگ برکتین
4
1 - دانشکده مهندسی کامپیوتر، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ایران
2 - دانشکده مهندسي برق، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ايران
3 - دانشکده مهندسي برق، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ايران
4 - دانشکده مهندسی کامپیوتر، واحد نجفآباد، دانشگاه آزاد اسلامی، نجفآباد، ایران
کلید واژه: آتاماتای سلولی کوانتومی, سامانه‌های کم‌مصرف, تکنیک انتشار پایانه ورودی, تمام جمع‌کننده,
چکیده مقاله :
با طراحی مدارها در ابعاد نانو و مشاهده مشکلات فناوری CMOS، طراحان به دنبال جایگزین¬های مناسب برای این فناوری هستند. آتاماتای سلولی کوانتومی QCA، یکی از این فناوری‌های پیشنهادی است که باتوجه‌به سرعت بالا و توان مصرفی پایین، توجه محققان را به خود جلب کرده است. از طرفی، روش ورودی انتشار گیت GDI یک روش بهبود توان و مساحت اشغالی است که با استفاده از تعداد ترانزیستور کمتر، منجر به‌سرعت بیشتر، اتلاف توان کمتر و كاهش پيچيدگي در توابع بولي شده است. همچنین جمع‌کننده به‌عنوان مدار محاسباتی پایه در طراحی سامانه‌های دیجیتال از اهمیت ویژه‌ای برخوردار است. در این مقاله، یک مدار نیم جمع¬کننده، یک مدار نیم تفریق¬کننده و سه مدار جمع‌کننده جدید در فناوری QCA و به کمک بلوک GDI بهبودیافته، طراحی شده است. شبیه‌سازی این مدارها با استفاده از نرم‌افزار QCADesigner و در فناوری 18 نانومتر مزیت‌های استفاده هم‌زمان از فناوری QCA و روش GDI به‌صورت هم‌زمان را نشان می¬دهد. نتایج حاصل از مقایسه و ارزیابی مدارهای پیشنهادی نسبت به بهترین جمع‌کننده موجود، بیانگر کاهش تا حدود 55% در مساحت اشغالی، کاهش محسوس تعداد سلول‌ها و تأخیری برابر و یا کمتر تا 28% نسبت به کارهای موجود است.
With the design of circuits at the nano-scale and observation of the problems of CMOS technology, designers are seeking suitable alternatives for this technology. Quantum-dot Cellular Automata (QCA) is one of these proposed technologies, which has attracted researchers' attention due to its high speed and low power consumption. On the other hand, the Gate Diffusion Input (GDI) method is an approach to improve power and area efficiency, which has led to higher speed, less power loss, and reduced complexity in Boolean functions through the use of fewer transistors. Furthermore, the adder, as a fundamental computational circuit in the design of digital systems, is of special importance. In this paper, a half-adder circuit, a half-subtractor circuit, and three new adder circuits in QCA technology have been designed and improved with the help of the GDI block. Simulation of these circuits using the QCADesigner software in 18-nanometer technology demonstrates the advantages of simultaneously using QCA technology and the GDI method. The results of the comparison and evaluation of the proposed circuits relative to the best existing adder indicate a reduction of about 55% in the occupied area, a significant decrease in the number of cells, and a delay that is equal to or less than 28% compared to existing works.
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