A New Coplanar Full Adder/Subtractor in Quantum-Dot Cellular Automata Technology

Subject Areas : Majlesi Journal of Telecommunication Devices

Mohsen Vahabi ¹ , Amir Sabbagh Molahosseini ²

1 - Department of Electrical Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran.
2 - Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran

Received: 2018-03-08 Accepted : 2018-04-04 Published : 2018-06-01

Keywords: en, Quantum-dot cellular Automata, coplanar (single layer), Full Adder/Subtractor,

Abstract :

The conventional CMOS technology faces different challenges such as fabrication in nanoscale which motivates researchers to find new alternatives to it for future high-performance systems. The quantum-dot cellular automata (QCA) is one of efficient nano-electronics technologies which can provide simple and efficient implementation of digital circuits in nanoscale. Due to the importance of addition in digital processors and embedded systems, there many QCA designs of adders and subtractors during the previous years. However, recently the unified design of adder and subtractor circuits has been considered to achieve overall area and delay reduction for digital computational circuits. In this paper, we present new coplanar design of a unified adder/subtractor unit with the QCA technology. Besides, the proposed single-layer design approach has been used to design separate half adder, half subtractor, half adder and full adder circuits. The comparison of circuit’s parameters of the proposed designs than previous works show the significant improvement in term of area, delay and cell number.

References:

[1] C.-H. Chang, A. S. Molahosseini, A. A. E. Zarandi, and T. F. Tay , "Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications", IEEE circuits and systems magazine, vol. 15, pp. 26-44, 2015.

[2] P. D. Tougaw and C. S. Lent, “Logical devices implemented using quantum cellular automata”, Journal of Applied physics, vol. 75, no. 3, pp. 1818–1825, 1994.

[3] H. Cho and E.E. Swartzlander,” Adder designs and analyses for quantum-dot cellular automata”, IEEE Transactions on Nanotechnology, 2007. 6(3): p. 374-383.

[4] J. Huang, M. Momenzadeh, et al. “Design and characterization of an and-or-inverter (AOI) gate for QCA implementation” , in Proceedings of the 14th ACM Great Lakes symposium on VLSI. 2004.

[5] S.-H. Shin, J.-C. Jeon, and K.-Y. Yoo, “Wire-crossing technique on quantum-dot cellular automata” , in NGCIT2013, the 2nd International Conference on Next Generation Computer and Information Technology, vol. 27, 2013, pp. 52–57.

[6] J.A. Fortes,“Future challenges in VLSI system design” , in VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on. 2003.

[7] S.E. Frost, A.F. Rodrigues, et al. Memory in motion:”A study of storage structures in QCA” , in First Workshop on Non-Silicon Computing. 2002.

[8] W. Wang, K. Walus, et al. “Quantum-dot cellular automata adders” , in Third IEEE Conference on. Nanotechnology, 2003.

[9] M. Kianpour and R. Sabbaghi-Nadooshan, “Optimized Design of Multiplexor by Quantum-dot CellularAutomata”, International Journal of Nanoscience and Nanotechnology, 2013. 9(1): p. 15-24.

[10] M.R. Beigh, M. Mustafa, et al., “Performance evaluation of efficient XOR structures in quantum-dot cellular automata (QCA)” . Circuits and Systems, 2013, 4, 147-156 2013.

[11] E.E. Swartzlander, H. Cho, et al. “Computer arithmetic implemented with QCA” , A progress report. in IEEE Conference Signals, Systems and Computers (ASILOMAR), 2010.

[12] S. Modi and A.S. Tomar. “Logic gate implementations for quantum dot cellular automata” , in Computational Intelligence and Communication Networks (CICN), 2010 International Conference on. 2010. IEEE.

[13] P.Z. Ahmad, F. Ahmad, et al., “A new F-shaped XOR gate and its implementations as novel adder circuits based Quantum-dot cellular Automata (QCA)” , IOSR Journal of Computer Engineering (IOSR-JCE), 2014. 16: p. 110-117.

[14] D. Abedi, G. Jaberipur, et al., “Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover” , IEEE Transactions on Nanotechnology, 2015. 14(3): p. 497-504.

[15] Peer Zahoor Ahmad, Firdous Ahmad, Syed Muzaffar Ahmad, Dr. Rafiq Ahmad Khan," Implementation of Quantum dot Cellular Automata based Novel Full Adder and Full Subtractor", International Journal of Science and Research (IJSR) ,p. 2319-7064, 2012.

[16] Shahidinejad A, Selamat A. “Design of First Adder/Subtractor using Quantum-Dot Cellular Automata” , Advanced Materials Research 2011; 403:3392–3397.

[17] J.I. Reshi and M.T. Banday. “Efficient Design of Nano Scale Adder and Subtractor Circuits using Quantum dot Cellular Automat” , in 2016 3rd International Conference on Electrical, Electronics, Engineering Trends, Communication, Optimization and Sciences (EEECOS). 2016.

[18] Y. Z. Barughi and S. R. Heikalabad, "A three-layer full adder/subtractor structure in quantum-dot cellular automata" , International Journal of Theoretical Physics, vol. 56, pp. 2848-2858, 2017.

[19] A.M. Chabi, A. Roohi, et al.,” Towards ultra-efficient QCA reversible circuits” , Microprocessors and Microsystems, 2017. 49: p. 127-138.

[20] D. Ajitha, K. V. Ramanaiah, P. Y. Kumar, and V. Sumalatha, "Efficient Design of 2'S complement Adder/Subtractor Using QCA" , in International Journal of Engineering Research and Technology, 2013.

[21] M. Gladshtein, "Design and simulation of novel adder/subtractors on quantum-dot cellular automata: Radical departure from Boolean logic circuits" , Microelectronics Journal, vol. 44, pp. 545-552, 2013.