Hardware Implementation of High-Speed Low-Power Viterbi Decoder for Deep-Space Communication

Subject Areas : Majlesi Journal of Telecommunication Devices

Ali  Ghasemi khah ¹ (Shahid Chamran university of Ahvaz)
Yosef  Seifi Kavian ² (Shahid Chamran university of Ahvaz)

Received: 2016-05-19 Accepted : 2017-01-13 Published : 2016-01-01

Keywords: Convolutional code, en, Viterbi Decoder, FPGA, Deep-Space Communication,

Abstract :

In communication systems, ensuring correct information reception is very important, Error Correction Coding methods have been developed in order to achieve this goal. Convolutional Code is used in Wireless, Satellite, mobile phones and Deep-Space communications, it is one of the most powerful Error Correction code, and the Viterbi algorithm is robust way to decode it. Power conception and speed are two important feature of Viterbi decoders, in many communications the power consumption is most important. In this paper, by removing extra decoding cycles, the SMU registers are reduced by 20%, the power consumption reduced by 14.5% and the speed increased 6 times without error correction performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan3, Xc3s400 FPGA chip.

References:

[1] U.Meyer-Baese, "Digital Signal Processing with Field Programmable Gate arrays ".Third Edition , Springer,pp. 418-436,2007

[2] H. Luke, " Signalubertragung". Springer, Heidelberg, 1988.

[3] P.Sweeney, Error Control Coding , Wiley, 2002.

[4] R.H. Morelos-Zaragoza, The Art of Error Correcting Coding, Wiley, 2002.

[5] S.Lin and D.J.Costello , "Error Control Coding".Prentice-Hall,pp. 315-348,1983.

[6] S.W.Shaker, S.H. Elramly, K.A. Shehata,"FPGA Implementation of a Reconfigurable Viterbi Decoder for WiMAX Receiver" IEEE 21st International Conference on Microelectronics, ICM 2009. Marrakech, Morocco, 19-22 December 2009.

[7] S.Ranpara and D.S. Ha, "A Low-Power Viterbi Decoder Design for Wireless Communications Applications",Int. ASIC conference,pp. 377-381, Washington, D.C ,Sept. 1999.

[8] M.Guo ,M.O.Ahmad,M.N.S.Swamy and C.Wang , "FPGA Design and Implementation of a Low-Power Systolic Array-Based Adaptive Viterbi Decoder" , IEEE Transactions on cicuit and system regular papers, Vol. 52, NO. 2,pp. 350-365, 2005.

[9] S.Ranpara, "On a Viterbi decoder design for low power dissipation,"M.Sc, Thesis, Virginia Polytechnic Institute and State University, 1999.

[10] F. Sun and T. Zhang, “Low-power State Parallel Relaxed Adaptive Viterbi Decoder,” IEEE Trans. Circuits and Syst. I, vol. 54, no. 5, pp. 1060-1068, May 2007

[11] M. D. Shieh, T. P. Wang, and D. W. Yang, “Low-power register-exchange survivor memory architectures for Viterbi decoders,” IET Circuit, Devices Syst. , vol.3, no.2, pp.83-90, April 2009

[12] C. C. Lin, Y. H. Shih, H. C. Chang, and C. Y. Lee, “Design of a Power-Reduction Viterbi Decoder for WLAN Applications,” IEEE Trans. Circuits and Syst. I, vol. 52, no. 6, pp. 1148-1156, June 2005

[13] B. Singh, S. Agarwal and T. Varma, “Hardware Implementation of Viterbi Decoder for Wireless Applications” International Journal of Computer Communication and Information System ( IJCCIS), Vol2. No1, ISSN: 0976–1349 July – Dec 2010

[14] J.Oh and M.Pedram., "Gated clock routing for low-power microprocessor design", IEEE Transactions on Computer-Aided Design,pp.715-722, 2001.

[15] F. Ghanipur and A. R. Nabavi, “Design of a Low-Power Viterbi decoder for wireless communication,” Electronics, circuits and systems, Dec 2003, pp 304 - 307 Vol.1, doi: 0-7803-8163-7/03/$17.00 0 2003 IEEE.

[16] Z. Navabi, "Digital System Test and Testable Design", springer, 2011.