Design of Current Starved Voltage Controlled Oscillator with Phase Locked Loop to Estimate the Process Corner Analysis
Subject Areas : Majlesi Journal of Telecommunication DevicesAnnamma k 1 , Sobhit Saxena 2 , Govind Singh Patel 3
1 - Research scholar, School of Electronics & Electrical Engineering. Lovely Professional University, Punjab, India
2 - School of Electronics & Electrical Engineering. Lovely Professional University, Punjab, India
3 - School of Electronics &Electrical Eng. ECE Dept, SITCOE, Yadrav, Kolhapur, Greater Noida, India
Keywords: VCO, PLL, Gain, Gale-or, Lector, Control Voltage, Current starved VCO, Oscillation Frequency, Sleepy Stack, Tuning Range,
Abstract :
This paper consists of a performance comparison of Current Starved Voltage Controlled Oscillator (CSVCO) for Phase Locked Loop (PLL). The design of Current Starved VCO is implemented using sleepy stack low power leakage technique. This has been implemented in 45nm CMOS Technology with a supply voltage of 0.45V in Cadence Software. The parameters such as average power, oscillation frequency, and delay are calculated in different process corners showing the performance of improvement results of cadence simulation. After comparison of the various parameters of PLL implemented with Sleep Stack CSVCO and Basic CSVCO, the sleepy stack approach is particularly useful in low power applications, The recommended PLL has a much smaller chip than previous designs, much lower power consumption and significantly higher efficiency. The proposed design of the PLL with Sleep Stack Technique makes the circuit efficiently to reduce sub-threshold leakage current, and achieves Frequency of 2.759 GHz, Power 2.559µw, phase noise -63.8(dBc/Hz) and Delay(µs) 0.0006544, respectively.
[1] M.Sivasakthi, P. Radhika, “Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 NM CMOS technology for the PLL application,” j.aeue.2023.154987, 2023.
[2] C.K. Pothina, N. P. Singh, J. L. Prasanna, C.Santhosh,. M.R Kumar, “Design of Efficient Phase Locked Loop For Low Power Applications”, doi.org/10.3390/2023.
[3] B. Singh, S. Kumar ,R. K. Chauhan, “Design of energy efficient VCO PLL Application Analog Integrated Circuits & Signal Processing”, 2023.
[4] K.B.Meena Kumari, G. Kavya, “Implementation of Digital Phase Locked loop”, Int.. Journal of Egg. Technology and Management Sciences, 2023.
[5] D.M..Ellaithy,Voltage-controlled oscillator-based analog-to-digital converter in 130-nm CMOS for biomedical applications” Journal of Electrical Systems and Information Technology, volume 10, 2023.
[6] kumar P. Chavan, R. Aradhya, “Design of 5.1GHz ultra low power and wide Tuning range Hybrid oscillator,” doi.org/10.11591/ijece. v13i4.pp:3778, 2023.
[7] R Gurjar, DK Mishra, “Design and performance analysis of low phase noise LC-voltage controlled oscillator”,doi.org/10.12928/telkomnika. v21i4.22341,2023.
[8] D. Ellaithy, “Voltage-controlled oscillator-based analog-to-digital converter in 130-nm CMOS for biomedical Applications” DOI:10.1186/s43067-023-00109-x,2023.
[9] P.Thool, J.D. Dhande, Y. A. Sadawarte, “A Review on Design and Analysis of Low Power PLL for Digital Applications and Multiple Clocking Circuits” ISSN: 2321-9653, 2022.
[10] K. Kasilingam, P. Balaiyah, P. Kumar Shukla,”Design of a high-performance advanced phase locked loop with high stability external loop filter”doi.org/10.1049/cds2.12130, 2022.
[11] T .Nirmalraj, , S .Radha krishnan, R. K .Karn, ,”Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology”. IEEE, 2022.
[12] T. Bao Phuc Ton,,C. Thinh Dang, “A Design of 45nm Low Jitter Charge Pump Phase-Locked Loop Architecture for VHF and UHF Fields” DOI: 10.21203/rs.3.rs-1804148/v1[4].B , 2022.
[13] S. Dhanush,T.N.Vaishnavi S. Parashar, “Design and Implementation of High Frequency and Low-Power Phase-locked Loop, U.Porto” Journal of Engineering DOI:10.24840/2183-6493_007.004_0006, 2021.
[14] P. Srivastava, R. Chandra Si. Chauhan,”Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45nmCMOSTechnology”, 2021.
[15] V. Kumar Sharma, “A survey of leakage reduction techniques in CMOS digital circuits for nano scale regime”, Australian Journal of Electrical & Electronics Engineering, DOI: 10.1080/1448837X.2021.1966957, 2021.
[16] B. Dharani, U. Nanda, “Impact of Sleepy Stack MOSFETs in CS-VCO on Phase Noise and Lock Performance of PLL”,DOI:10.1007/s633-021-01446-0, 2021.
[17] Kumar Tiwari,” Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method”, (IJRASET) , 2021.
[18] R.Prithiviraj, J.Selva kumar , “Design and Analysis of Low power and High Frequency Current Starved Sleep voltage Controlled Oscillator for Phase Locked Loop Applications”, DOI:10.1007/s020-00619-7, 2021.
[19] S. Rani, M. Vinothkumar, K. Krishnamoorthy, “Design of low power VCO using FinFET technology for biomedical applications. Materials Today”: Proceedings, 45, pp.2145–2151. 10.1016/j, 2021.
[20] M. Maiti, S. Kumar Saw, A. J. Mondal, A. Majumder, “A hybrid design approach of PVT tolerant, power efficient ring VCO” doi. org /10. 1016/ j.asej. 2019. 10.009, 2020.
[21] U.Nanda, D.P.Acharya, and D. Nayak,. “Process Variation Tolerant Wide-band Fast PLL with Reduced Phase Noise using Adaptive Duty Cycle Control Strategy”. International Journal of Electronics.2020
[22] Sh.Askari, M.Saneei, “Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications” ,doi.org/10.1002/cta.2582, 2018.
[23] B.S.Choudhury, S.Maity “A low phase noise cmos ring vco for short range device application. In: Conf. proceedings", EESCO-IEEE, 2015.
[24] N. Pathak, R. Mohan, “Phase Locked Loop Design and Implementation using Current Starved Voltage Controlled Oscillator “/IJERTV3IS2074, 2014.
[25] H .Malviya, S. Nayar C. Roy “A New Approach FOR Leakage Power Reduction Techniques in Deep Sub micron Technologies in CMOS Circuit for VLSI Applications” Computer Sci Software Eng. 25, 2013.
[26] PK. Pal, R.S. RathoreAK. , Rana, G. Saini, “New low power techniques: Leakage feedback with stack & sleep stack with the keeper”. In: ICCCT-2010. IEEE. pp.296–301.2010.
[27] J. C. Park and V. J. M. III, “Sleepy stack leakage reduction,” IEEE Trans. Very Large Scale Integrate. (VLSI) Syst., vol. 14, pp. 1250- 1263, 2006.
[28] J. Ch. Park, “Sleepy stack: a new approach to low power VLSI logic and memory”, School of electrical and computer engineering, Georgia institute of technology, 2005.
Majlesi Journal of Telecommunication Devices Vol. 13, No. 3, September 2024
K. Annamma1
,Sohbit Saxena2 ,Govin Singh Patel3
1- Research scholar, School of Electronics & Electrical Engineering. Lovely Professional University, Punjab, India.
Email: anusasmi@gmail.com (Corresponding author)
2- School of Electronics & Electrical Engineering. Lovely Professional University, Punjab, India.
Email : sobhit.23364@lpu.co.in
3- School of Electronics &Electrical Eng. ECE Dept, SITCOE, Yadrav, Kolhapur, Greater Noida, India.
Email: govindpatel1104@gmail.com
ABSTRACT: This paper consists of a performance comparison of Current Starved Voltage Controlled Oscillator (CSVCO) for Phase Locked Loop (PLL). The design of Current Starved VCO is implemented using sleepy stack low power leakage technique. This has been implemented in 45nm CMOS Technology with a supply voltage of 0.45V in Cadence Software. The parameters such as average power, oscillation frequency, and delay are calculated in different process corners showing the performance of improvement results of cadence simulation. After comparison of the various parameters of PLL implemented with Sleep Stack CSVCO and Basic CSVCO, the sleepy stack approach is particularly useful in low power applications, The recommended PLL has a much smaller chip than previous designs, much lower power consumption and significantly higher efficiency. The proposed design of the PLL with Sleep Stack Technique makes the circuit efficiently to reduce sub-threshold leakage current, and achieves Frequency of 2.759 GHz, Power 2.559µw, phase noise -63.8(dBc/Hz) and Delay(µs) 0.0006544, respectively.
KEYWORDS: VCO, PLL, Gain, Gale-or, Lector, Control Voltage, Current starved VCO, Oscillation Frequency, Sleepy Stack, Tuning Range.
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1. Introduction
The Phase Locked Loop (PLL) is a control system used to generate the phase of output signal which is related to the phase of the input signal. The major blocks present in the PLL are Voltage controlled Oscillator and phase detector in a feedback loop. This paper depicts one of the major blocks called VCO. The main functionality of the VCOs is in the communication systems. Among the multiple types of VCOs, the ring oscillators and LC oscillators plays a major role in terms of high frequency, less noise, wide tuning range [1], and the area occupancy. The LC VCO which consists of an induct-or and capacitor occupies more area. The ring oscillators consist of the delay cells which have the same functionality similar to the buffer and these cells would occupy more area. In a ring oscillator, the last delay cell output is connected to the first delay cells input [2], which is called feedback. The delay cells can be either single ended or differential accordingly [4]. The increase in the number of delay cells give rise to consumption of area [6]. Because of the differences in the driving capability, the characteristics of the VCO become nonlinear which can be avoided by adding feedback circuit. By adding this feedback circuit, it further leads to the increase in cost of the circuit [7]. The current starved VCO technique was designed in order to overcome the disadvantages caused by the previous VCO’s [7].
Fig. 1. Schematic diagram for PLL with Sleep Stack Current Starved VCO.
This paper is organized as follows. Section2 explains basic Current Starved VCO. Section 3 describes different leakage power reduction techniques in CMOS circuits. Section 4 defines simulation results and design comparisons. Finally, section 5 concludes this paper.
2. CURRENT STARVED RING VCO WITH SLEEP STACK & KEEPER TECHNIQUE
Fig. 2. Current Starved Ring VCO with Sleepy Stack & Keeper Technique Circuit.
The sleepy stack approach is particularly useful in low-power applications or when power efficiency is a critical design consideration. It helps to reduce power consumption without sacrificing the speed or performance of the circuit. The purpose of the alternative arrangement in the proposed circuit is to reduce the number of transistors and the area utilization. The alternative arrangement of the proposed design itself makes the circuit works efficiently to reduce sub-threshold leakage current, which in turn reduces power consumption. Therefore, not all the delay cells in the proposed design need to be connected with the sleepy stack approach.
3.CURRENT STARVED VCO PLL ARCHITECTURE WITH SLEEP STACK TECHNIQUE
Among the different types of VCO's, ring oscillator is the efficient in terms of frequency and driving capabilities. The ring VCO has been designed with delay stage. When these delay stages increased, lead to the non-linearity of the circuit. This non- linearity can be overcome by increasing the number of delay cells which has increased the complexity of the circuit and also increasing the power consumption [8]. The output frequencies of a basic VCO are controlled by the control voltage whereas the current is controlled by the current starved VCO [9]-[10]. The circuit consists of delay cells along with the current mirror which is used to limit the current to all the delay cells. The current starved VCO alone has also increased the leakages and power consumption [1]. These leakages can be further reduced by applying the low leakage techniques to the delay cells and by varying the aspect ratio of transistors which reduces the threshold voltage of basic current starved VCO [11].
Fig.3. PLL Architecture with current starved VCO.
Fig. 3.1. Schematic diagram for Current Starved VCO.
In order to avoid this power consumption, a VCO named current starved was designed. The output frequencies of a basic VCO are controlled by the control voltage whereas the current is controlled by the current starved VCO [9]-[10]. The circuit consists of delay cells along with the current mirror which is used to limit the current to all the delay cells. The current starved VCO alone together has also increased the leakages and power consumption [1]. These leakages can be further reduced by applying the low leakage techniques to the delay cells and by varying the aspect ratio of transistors which reduces the threshold voltage [11].
4. Leakage reduction techniques implemented in VCO
The basic CSVCO, Current Starved Voltage Controlled Oscillator, is operated with the input voltage namely control voltage (Vctrl). As the Vctrl decreases, the current that is to be mirrored from the transistor M1 reduces when it is passed through the different PMOS in the delay stages. Because of the active mode of transistors in the CSVCO, the leakage power has been increased [1]. In this paper, the current starved VCO has been implemented with different low power leakage techniques like Gale-or, Lector, Sleepy Keeper, Sleep Stack, and Sleepy Stack to observe the better performance of the circuit [12]. Performance analysis can be observed in terms of different parameters like frequency, delay, and average power is calculated in different process corners showing the improved performance Phase Locked Loop, For different applications
.4.1. Current Starved VCO with Sleep Stack Technique
The CSVCO circuit is implemented with Stack technique as shown in Figure 6, in which both the stack and sleep techniques are implemented above and below the pull -up and pull-down network, respectively. In normal mode, the sleep transistor would go to sleep mode, then the stack transistors reduce the leakages [24]-[26]. In case of the active mode, the sleep transistor becomes ON and stack transistors are OFF, reducing the leakages in CSVCO circuit.
Fig. 4. CSVCO using Sleepy Stack Technique.
5. Process corner analysis
Corner analysis provides a convenient way to measure circuit performance while simulating a circuit with sets of parameter values that represent the most extreme variations in a manufacturing process. All the proposed circuits with different low leakage techniques have their average power, oscillating frequency, and tuning range calculated in process corners like nominal, slow-fast, fast-slow, fast-fast and slow-slow conditions.
The mobility and the threshold voltage which in turn effect the device performance. If the threshold voltage is lowered, then there is more current and effectively the device is faster, however, if the threshold voltage is increased there is less current and the device could be slower. A lower supply voltage causes slower switching of the gates and results into an overall slower circuit, a high supply voltage drives faster switching of the larger gates which makes the circuits faster.
In addition to temperature and voltage analysis, the process corner analysis is carried out with the Cadence Virtuoso tool using the 45 NM generic process design kit (GPDK) technology file at 27℃ (fig.5).
Fig. 5. Corner Analysis of Pavg for CSVCO applied with different low leakage techniques.
From the above plotted graph, it is observed that the average power in all the corners remained almost constant and in the Sleep Technique is always low in all the corners.
Fig. 5.1. Corner Analysis of Oscillating Frequency (GHz) for CSVCO applied with different low leakage techniques.
From the above plotted graph, it is observed that the oscillation frequency in all the corners remained low and, in the Gale,-or Technique is significantly reduced in all the corners.
From the below plotted graph, it is observed that the frequency tuning range calculated in percentage for all the corners in case of Sleep technique remained high and in the Lector Technique it is significantly reduced in all the corners.
Fig.5.2. Corner analysis plot of Frequency Tuning Range (%) for CSVCO applied with different low leakage techniques.
6. SIMULATION AND RESULT ANALYSIS
To analyze the circuit and to perform the simulation results of the CSVCO implemented different low leakage techniques, the circuits has been implemented in virtuoso tool in Cadence Software in 45nm technology with a supply voltage of 0. 45V.The simulated output of the oscillator is obtained by initializing setting the output node to either 1 or 0 to get the proper oscillations. The parameters like average power (Pavg),delay, Oscillation frequency and gain are calculated at a room temperature of27℃ and with a control voltage of 0.45V.
Table 1. Simulation results for parameters with different low leakage power techniques in CSVCO.
S. No. | Low Leakage Power Techniques | Average Power (W) | Area (μm2) | Delay (μs) | Frequency (GHz) | Gain (Ghz/V) | Tuning Range (%) | |
1 | Gale-or | 48.20 e-9 | 37.5769 | 19.56 | 13.81 | 3.07 | 56.21 | |
2 | Lector | 49.77 e-9 | 35.581225 | 32.25 | 14.34 | 3.19 | 6.07 | |
3 | Sleep | 40.45 e-12 | 26.3169 | 327.8 | 72.11 | 16.02 | 98.76 | |
4 | Stack | 49.56 e-9 | 56.4001 | 19.03 | 30.45 | 6.76 | 14.71 | |
5 | Sleep Stack | 58.32 e-9 | 37.5769 | 0.4896 | 58.89 | 13.87 | 34.86 | |
Fig. 6. Parameter analysis of CSVCO with different low leakage power techniques.
Table 2. Comparison analysis of PLL CSVCO VS sleep stack PLL CSVCO.
Parameters | PLL with basic CSVCO | Proposed work- PLL with SLEEP STACK CSVCO
|
VCO type | Ring | Ring |
Tech (NM) | 45 | 45 |
Freq (GHz) | 2.592 | 2.759 |
Supply volt(v) | 1 | 1 |
Power (MW) | 0.002686 | 0.002559 |
P-Noise(dBc/Hz) | -72.2 | -63.8 |
Delay(µs) | 0.866 | 0.0006544 |
From the above table and simulation result of parameter analysis with low leakage power techniques, the current starved VCO with sleep stack and keeper technique overcome the challenges present in the existing VCO in wide tuning, high frequency applications. Also, these challenges include leakage power, phase noise and limited frequency range. To ensure its robustness, extensive simulations are performed under extreme conditions such as different process corners, varying control voltage, and at extreme temperatures. The proposed CSVCO PLL circuit consumes less power. It achieves 20 % improvement in oscillation frequency because of the pull-up sleepy and pull-down sleepy stack transistor arrangement. The frequency tuning range of the proposed circuit also exhibits 27 % improvement. It also achieves less delay with the phase noise and FOM improvement of 17.29 % and 10.74 % ,respectively.
Fig. 7. Comparison analysis of PLL CSVCO & Sleep Stack PLL CSVCO.
The above figure confirms the robustness of the proposed design, making it a promising solution for high-frequency applications. These improvements are achieved at a supply voltage of 1 V. To ensure the stability of the circuit, Monte-Carlo analysis also conducted for various parameters. From the obtained results, it is concluded that the proposed design outperforms existing works in various performance parameters and it is highly suitable for PLL applications including wireless communication and radio frequency.
7.Conclusions and future scope
From the above tabular column and the graphs plotted it is observed that all the low leakage power techniques applied to the existing CSVCO are better in one or the other parameter like average power, oscillation frequency, delay and the gain. It is also observed that as the temperature is increased from corner analysis 27℃ to 80℃then the power and delay are increased and they are decreased when the temperature is decreasedto-40℃.
After comparing the various parameters of PLL implemented with Sleep Stack CSVCO and Basic CSVCO, it is observed that Sleep Stack has better performance. To achieve further, higher frequencies vary the supply voltage and the number of stages in the CSVCO from 5 stages to 7,9,11 and so on, but with increase in other parameters like area and power.
References
[1] M.Sivasakthi, P. Radhika, “Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 NM CMOS technology for the PLL application,” j.aeue.2023.154987, 2023.
[2] C.K. Pothina, N. P. Singh, J. L. Prasanna, C.Santhosh,. M.R Kumar, “Design of Efficient Phase Locked Loop For Low Power Applications”, doi.org/10.3390/2023.
[3] B. Singh, S. Kumar ,R. K. Chauhan, “Design of energy efficient VCO PLL Application Analog Integrated Circuits & Signal Processing”, 2023.
[4] K.B.Meena Kumari, G. Kavya, “Implementation of Digital Phase Locked loop”, Int.. Journal of Egg. Technology and Management Sciences, 2023.
[5] D.M..Ellaithy,Voltage-controlled oscillator-based analog-to-digital converter in 130-nm CMOS for biomedical applications” Journal of Electrical Systems and Information Technology, volume 10, 2023.
[6] kumar P. Chavan, R. Aradhya, “Design of 5.1GHz ultra low power and wide Tuning range Hybrid oscillator,” doi.org/10.11591/ijece. v13i4.pp:3778, 2023.
[7] R Gurjar, DK Mishra, “Design and performance analysis of low phase noise LC-voltage controlled oscillator”,doi.org/10.12928/telkomnika. v21i4.22341,2023.
[8] D. Ellaithy, “Voltage-controlled oscillator-based analog-to-digital converter in 130-nm CMOS for biomedical Applications” DOI:10.1186/s43067-023-00109-x,2023.
[9] P.Thool, J.D. Dhande, Y. A. Sadawarte, “A Review on Design and Analysis of Low Power PLL for Digital Applications and Multiple Clocking Circuits” ISSN: 2321-9653, 2022.
[10] K. Kasilingam, P. Balaiyah, P. Kumar Shukla,”Design of a high-performance advanced phase locked loop with high stability external loop filter”doi.org/10.1049/cds2.12130, 2022.
[11] T .Nirmalraj, , S .Radha krishnan, R. K .Karn, ,”Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology”. IEEE, 2022.
[12] T. Bao Phuc Ton,,C. Thinh Dang, “A Design of 45nm Low Jitter Charge Pump Phase-Locked Loop Architecture for VHF and UHF Fields” DOI: 10.21203/rs.3.rs-1804148/v1[4].B , 2022.
[13] S. Dhanush,T.N.Vaishnavi S. Parashar, “Design and Implementation of High Frequency and Low-Power Phase-locked Loop, U.Porto” Journal of Engineering DOI:10.24840/2183-6493_007.004_0006, 2021.
[14] P. Srivastava, R. Chandra Si. Chauhan,”Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45nmCMOSTechnology”, 2021.
[15] V. Kumar Sharma, “A survey of leakage reduction techniques in CMOS digital circuits for nano scale regime”, Australian Journal of Electrical & Electronics Engineering, DOI: 10.1080/1448837X.2021.1966957, 2021.
[16] B. Dharani, U. Nanda, “Impact of Sleepy Stack MOSFETs in CS-VCO on Phase Noise and Lock Performance of PLL”,DOI:10.1007/s633-021-01446-0, 2021.
[17] Kumar Tiwari,” Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method”, (IJRASET) , 2021.
[18] R.Prithiviraj, J.Selva kumar , “Design and Analysis of Low power and High Frequency Current Starved Sleep voltage Controlled Oscillator for Phase Locked Loop Applications”, DOI:10.1007/s020-00619-7, 2021.
[19] S. Rani, M. Vinothkumar, K. Krishnamoorthy, “Design of low power VCO using FinFET technology for biomedical applications. Materials Today”: Proceedings, 45, pp.2145–2151. 10.1016/j, 2021.
[20] M. Maiti, S. Kumar Saw, A. J. Mondal, A. Majumder, “A hybrid design approach of PVT tolerant, power efficient ring VCO” doi. org /10. 1016/ j.asej. 2019. 10.009, 2020.
[21] U.Nanda, D.P.Acharya, and D. Nayak,. “Process Variation Tolerant Wide-band Fast PLL with Reduced Phase Noise using Adaptive Duty Cycle Control Strategy”. International Journal of Electronics.2020
[22] Sh.Askari
, M.Saneei, “Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications” ,doi.org/10.1002/cta.2582, 2018.[23] B.S.Choudhury, S.Maity “A low phase noise cmos ring vco for short range device application. In: Conf. proceedings", EESCO-IEEE, 2015.
[24] N. Pathak, R. Mohan, “Phase Locked Loop Design and Implementation using Current Starved Voltage Controlled Oscillator “/IJERTV3IS2074, 2014.
[25] H .Malviya, S. Nayar C. Roy “A New Approach FOR Leakage Power Reduction Techniques in Deep Sub micron Technologies in CMOS Circuit for VLSI Applications” Computer Sci Software Eng. 25, 2013.
[26] PK. Pal, R.S. RathoreAK. , Rana, G. Saini, “New low power techniques: Leakage feedback with stack & sleep stack with the keeper”. In: ICCCT-2010. IEEE. pp.296–301.2010.
[27] J. C. Park and V. J. M. III, “Sleepy stack leakage reduction,” IEEE Trans. Very Large Scale Integrate. (VLSI) Syst., vol. 14, pp. 1250- 1263, 2006.
[28] J. Ch. Park, “Sleepy stack: a new approach to low power VLSI logic and memory”, School of electrical and computer engineering, Georgia institute of technology, 2005.
Paper type: Research paper
Received: 19 April 2024; revised: 7 June 2024; accepted: 16 May 2024; published: 14 July 2024
How to cite this paper: K. Annamma ,S. Saxena ,G. Singh Patel, “Design of Current Starved Voltage Controlled Oscillator with Phase Locked Loop to Estimate the Process Corner Analysis”, Majlesi Journal of Telecommunication Devices, Vol. 13, No. 3, pp. 151-158 2024.
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