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Article Type: Original Research

A Novel Design of an Active Low 2:4 Decoder using Quantum-Dot Cellular Automata

Subject Areas : Journal of Optoelectronical Nanostructures

Reza Pourtajabadi ¹ , Maryam Nayeri ² , Mohamad Reza Shayesteh ³

1 - Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran
2 - Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran
3 - Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran

Received: 2025-06-23 Accepted : 2025-06-23 Published : 2025-06-23

Keywords:

Abstract :

Quantum-dot cellular automata (QCA) is a nanoscale technology with unique features compared to the silicon-based technology that has been recently used in the design of combinational and sequential logic circuits. Today, QCA is a well-known technology for the design of digital systems and provides a modern pattern for information processing and communication with higher speed, higher integration scale, higher switching frequency, and less power consumption compared to silicon-based technology. In this paper, the QCA technology is used to design an active-low 2:4 decoder using an active-high decoder. The initial scheme is optimized and an independent active-low decoder is presented. In the optimized structure, the number of cells, and the occupied space are decreased significantly followed by power consumption reduction and an increase in the output signal level compared to the initial scheme. The number of required clock phases to generate the output is also reduced to three. Design and simulation are carried out in QCA Designer.

References:

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Islamic Azad University

Journal of
Optoelectronical Nanostructures

Winter 2021 / Vol. 6, No. 1

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Research Paper

A Novel Design of an Active Low 2:4 Decoder using Quantum-dot Cellular Automata

Reza Pourtajabadi1, Maryam Nayeri*,2, Mohamad Reza Shayesteh3

1Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran.

2Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran.

3Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran.

Received:

Revised:

Accepted:

Published:

Abstract

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Keywords:

quantum-dot cellular automaton, majority voter gate, active low decoder, combinational circuit, coplanar architecture.

1. INTRODUCTION

Today, moving towards nanotechnology is inevitable due to CMOS limitation constraints. Although reducing the dimensions increases the computational power, results in some problems, including the internal connections due to dimension miniaturization, high leakage current, and inefficient power distribution [1]. So, semiconductor-based transistors are hard to miniaturize. considering the supply voltage reduction, power loss resulting from leakage current and internal connections is a great challenge for transistor circuits. Thus, nanotechnology is an alternative solution to resolve these problems [2-5]. After introducing QCA in 1993 [6], various devices were developed using this technology. Recent studies show that QCA can achieve high switching speed, high-density circuits, and operation at room temperature [7]. The developments of modeling using Spice and verification of QCA capabilities indicate the continuous attractiveness of this technology. Recently, various molecular QCA models have been implemented, and their power is analyzed [8].

Among the practical applications of quantum dots technology, we can mention such as highly efficient photovoltaic solar cells [9], optoelectronic devices – lasers [10], optical amplifiers [11], single-photon sources [12], and photo detectors [13].

In this technology, computations using cellular automata are based on an array of quantum-dot devices. QCA is not the only nanoscale solution to resolve these problems, and it provides novel techniques for computations and data transmission [14].

The QCA technology is a tool for presenting the binary information of the cell that does not have current flow and the device operates by coupling the cells as a result of an electromagnetic field. Based on the unique property of this technology, logical states are not stored like the conventional electronic industry, but they are presented by a nanoscale cell that can encode data regarding the position of the electrons. QCA transmits data using the clocking technique that operates based on increasing or decreasing the tunneling barrier [15].

This paper is given the following structure: Section 2 describes the first principles of QCA. A decoder is presented in Section 3. Section 4 presents the proposed active-low QCA decoder and its optimal scheme. Section 5 presents the simulation results and examines the performance of the decoder. Finally, the paper is concluded.

2. Principle of QCA

A cell is required to construct QCA devices. Each cell is comprised of a nanoscale square structure including four quantum dots at four corners and two free electrons [16]. The electrons cannot tunnel between neighbour cells, while they can tunnel between the adjacent points of a cell. Inserting two electrons in one cell results in Columbic interaction as a result of which the two electrons are configured diagonally with maximum distance from each other. The square QCA cell has only two diameters indicating two steady states of the electron configuration, called the electron polarization. Fig. 1 shows two possible configurations of QCA cell with stable polarization of P=+1 and P=-1, indicating the logic “1” and “0”.

Fig. 1. QCA cell polarization

A. QCA Implementation Techniques

There exist four distinct classifications of QCA cells, contingent upon the materials employed in their construction.

1) Metal QCA

The metallic QCA cell is comprised of four aluminum dots designated as D1 through D4, which are interconnected via aluminum oxide tunnel junctions and associated capacitors [17]. The dots E1 and E2 function as Single Electron Transistor (SET) electrometers for the purpose of output detection. An illustration of the cell is provided in Fig. 2 [18]. The metal-based QCA latch has been realized and showcased in Reference [19], where it was operated at a temperature of 70mK.

Fig. 2. Metal QCA cell (a) a streamlined schematic representation of a four-dot metal QCA cell (b) scanning electron microscopy image of the aforementioned QCA cell [18].

2) Molecular QCA

is regarded as a highly promising approach for the realization of QCA circuits. This technology functions effectively at ambient temperature while exhibiting a high device density and rapid operational speed. The configuration of the Molecular QCA cell is delineated in Reference [20]. The encoding of binary information occurs through specific charge arrangements. The representation of the Molecular QCA cell is illustrated in Figure 3 [21].

Fig. 3. Three states of six dot molecular QCA [21]

3) Semiconductor QCA

Semiconductor materials like InAs/GaAs and GaAs/AlGaAs are employed in the production of quantum dots [22]. QCA cells can be constructed utilizing the same cutting-edge complementary metal-oxide-semiconductor (CMOS) technology that utilizes these semiconductor materials. The polarization of a cell is contingent upon the distribution of charge, and the computational process occurs through the interaction or coupling between a cell and its adjacent cells.

Fig. 4. The physical representation of the semiconductor QCA cell.

4) Magnetic QCA

The magnetic realization of QCA was introduced by Cowburn and Welland [23]. A nanomagnet, comprising a singular circular nanodot, serves as the QCA cell. These nanodots, constructed from magnetic supermalloy, are arranged in a linear configuration, and an oscillating magnetic field is applied to the dot. The magnetic QCA cell demonstrates functionality at ambient temperature. An illustration of a three-input majority gate within the magnetic QCA framework is presented in Fig. 5.

Fig. 5. Binary logical representation within magnetic QCA. (a) Logical state ‘1’, (b) Logical state ‘0’, and (c) Absence of state.

B. QCA Majority Logic Gate

The QCA structures are formed by configuring the cells beside each other. A wire is formed by putting cells one after the other. QCA cells tend to spend a minimum amount of energy on each other. Therefore, the adjacent cells influence each other and the input signal propagates to the output and each cell tracks the polarization wire of its previous cell, considering the cell configuration. Signal transmission via binary wire is shown in Fig. 6. Unlike other devices, QCA wires have a very low energy loss, because no electric current passes the cells [24].

Fig. 6. Signal propagation in binary wires.

Fig. 7 shows the inverter gate used in this study. This gate converts binary “1” to “0” and vice versa.

The main element in the QCA circuits is the three-input majority voter gate, which is shown in Fig. 4 and is described by Equation (1). The majority logic based on the induction method can reduce the time constraint and complexity of the QCA circuit [25].

Fig. 7. Cell inverter gate.

The three-input majority value affects the polarization of the central cell and generates an output. To implement the above gate in CMOS technology, 26 resistors are required, but in QCA technology, the MV¹3 gate can be implemented by 5 cells. As shown in Fig. 8, using the majority voter gate, two-input AND gate and two input OR gate are achieved. To construct the AND gate, one input is fixed to “0” like Eq. (2), and to construct the OR gate, one input is fixed to “1” as in Eq. (3).

Fig. 8. a) Majority voter gate. b) OR gate. c) AND gate.

(1)

(2)

(3)

The QCA circuits are divided into four sections that are excited and set up by four phases of the clock signal. As shown in Fig. 9, each clock has a phase difference of 90 degrees with the subsequent clock. In each area, the clock has four states, including high, high to low, low, and low to high. In the high to low state, the cell starts calculation, and in the low state, the cell value is fixed. When the clock phase changes from low to high, the cell loses its value, and in the high state, the cell is inactive [26]. The cell in each area demonstrates a behaviour similar to a latch.

Fig. 9. QCA clocking.

3. Decoder

Decoders play an essential role in computer architecture. They are used in different sections like RAM² or lookup tables [27]. A decoder is a device that selects one of the output lines after activation. Most decoders have n inputs and 2n outputs. Decoding is essential in applications like multiplexing, 7-segments, and memory address decoders.

The block diagram of an active-low 2:4 decoder is shown in Fig. 10. In this diagram, four AND gates and six inverter gates are used; an inverter gate is inserted at the output of each AND gate. The outputs O1 to O4 of the decoder are obtained based on Eq. (4) to Eq. (7).

(4)

(5)

(6)

(7)

$E:\AX\decoder block.png$

Fig. 10. Active low 2:4 decoder block diagram

Table I also represents the true table of the active-low decoder.

TABLE I

Truth Table of an active high 2:4 decoder.

Output				Input
O1	O2	O3	O4	B	A
0	1	1	1	0	0
1	0	1	1	1	0
1	1	0	1	0	1
1	1	1	0	1	1

4. Proposed decoder

In this scheme, four MV3 gates are used. One input of each majority voter fate is fixed on logic “0” with P=-1, as a result of which it operates like an AND gate. To invert the input A at MV3 1 and 2 and invert the input B at MV3 1 and 3 (according to Table I), two-cell inverter is used that reduces the number of cells and the occupied area of the circuit. To invert each output, a two-cell inverter is inserted at the output of each majority voter gate.

$E:\AX\actve low noti.png$

Fig. 11. First proposed circuit of a 2:4 active low decoder.

The maximum number of cells in one clock area of the proposed circuit is 21, and the number of QCA cells of the proposed circuit is 102. Fig. 11 shows the initial circuit.

Since inserting an inverter gate at the output of each MV3 reduces efficiency, increases power consumption, increases the number of cells and occupied area, and reduces the output signal level. In the optimized circuit, without inserting an inverter gate at the output of each MV gate and by changing the polarization of the fixed cell, all four MV3 gates of the corresponding active-high decoder change from P=-1 to P=+1 and the binary value changes from “0” to “1”, and finally the AND gates are converted to OR gates. The optimal active-low decoder is shown in Fig. 12.

$E:\AX\2to4 orig active H - Copy.png$

Fig. 12. Optimized circuit of a 2:4 active low decoder.

5. Result and discussion

The proposed circuit is comprised of 94 cells, demonstrating an 8% reduction compared to the initial scheme. Reducing the number of cells reduces the occupied area of the circuit, increases the output signal level, and decreases the power consumption. The occupied area and the output signal level of the optimized circuit are improved by 20% and 40%, respectively compared to the initial structure. Fig. 13 shows the simulation results of the optimized active-low decoder. The output of this circuit is generated after three clock phases. According to the simulation results, for each input, only one of the outputs is “0” and the other outputs are “1”, demonstrating the correct operation of the circuit.

$E:\AX\active low result low cell orig.png$

Fig. 13. Simulation result of the optimized circuit.

Table II compares the proposed method and the scheme presented in Ref [28-30]. Comparison is made based on the number of cells, occupied area, number of gates, and number of clock phases to generate output, indicating improved performance compared to the previous scheme.

TABLE II

Comparison between the proposed circuit and ref [25-27]

Proposed in[30]	Proposed in[29]	Second Proposed in [28]	First Proposed in[28]	Proposed Circuit
137	212	159	110	94	Cell Count
0.15	0.25	0.177	0.13	0.082	Area Covered (um2)
4	6	4	4	4	Number of Gate
5	6	3	3	3	Clock Phases

Table III shows the percentage improvement achieved in term of Cell count and Area Covered compared to previous schemes in Ref [28-30].

TABLE III

Percentage Improvement Compared to ref [25-27].

Proposed in[30]	Proposed in[29]	Second Proposed in [28]	First Proposed in[28]
31	55	40	15	Cell Count
45	67	53	37	Area Covered

6. Conclusion

Decoding and encoding play an essential role in communication systems. In this paper, first, a new active-low 2:4 decoder is designed using QCA technology. Then, it is optimized considering the QCA characteristics. In the optimized circuit, the number of cells is reduced as a result of which the occupied area on the chip and the power consumption is reduced. Another characteristic of the optimized scheme is that without changing the circuit structure, and by changing the polarization of the fixed cells, the active-low decoder changes to active-high. The optimized circuit is comprised of 94 cells in an approximate area of 0.08um2, indicating a significant improvement compared to previous schemes. Also, one of the important advantages of the presented circuit is using the simplest inverter gate (two-cell inverter) and achieving a high signal level. In future studies, the presented decoder can be combined to develop larger decoders. The circuit layout and its performance are performed using QCA Designer.

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[1] Majority voter gate

[2] 1 Random access memory

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A Novel Design of an Active Low 2:4 Decoder using Quantum-Dot Cellular Automata