Device and Circuit Performance Simulation of a New Nano- Scaled Side Contacted Field Effect Diode Structure

Subject Areas : Journal of Optoelectronical Nanostructures

Omid Talati Khoei ¹ (Department of Electrical Engineering, Khoy Branch, Islamic Azad University, Khoy, Iran)
Reza Hosseini ² (Department of Electrical Engineering, Khoy Branch, Islamic Azad University, Khoy, Iran)

Received: 2019-04-06 Accepted : 2019-07-23 Published : 2019-08-01

Keywords: On-State, Off-State, Logic Gates, Propagation Delay, Static Power Dissipation, Power Delay Product,

Abstract :

A new side-contacted field effect diode (S-FED) structure has been
introduced as a modified S-FED, which is composed of a diode and planar double gate
MOSFET. In this paper, drain current of modified and conventional S-FEDs were
investigated in on-state and off-state. For the conventional S-FED, the potential barrier
height between the source and the channel is observed to become larger and the flow of
injected electrons is reduced. Thus, the drain current decreases in on-state. While in offstate,
the potential barrier height and width become smaller in conventional S-FED and
so the drain current is greater than that of modified structure. Mixed mode simulations
were used to determine the performance of the proposed logic gates. We compared the
operation of modified S-FED with that of conventional S-FED. Simulated power delay
product (PDP) of the modified S-FED-based NOR, NAND, XOR gates were found to
be about 416fJ, 408fJ and 336fJ, respectively, compared with 906fJ, 810fJ and 705fJ
achievable with conventional S-FED logic gates.

References:

[1] M. Roohy, R. Hosseini. Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor, Journal of Optoelectronical Nanostructures. 4(2) (2019) 13-28.
Available: http://jopn.miau.ac.ir/article_3475.html
[2] M. H. Han, Ch.Y. Chang, H. B. Chen, Y. Ch. Cheng, Y. Ch. Wu. Device and Circuit Performance Estimation of Junctionless Bulk FinFETs, IEEE
NOR
NAND
XOR
Power Dissipation [nW]
260
240
224
Propagation Delay [ps]
1.6
1.7
1.5
Power Delay Product[fJ]
416
408
336
NOR
NAND
XOR
Power Dissipation [nW]
195
180
168
Propagation Delay [ps]
4.65
4.5
4.2
Power Delay Product[fJ]
906
810
705
Transaction on Electron Devices. 60(6) (2013) 1807-1813.
Available: https://ieeexplore.ieee.org/document/6509427
[3] A. Pourchitsaz, M. R. Shayesteh, Self-heating effect modeling of a carbon nanotube-based fieldeffect transistor (CNTFET), Journal of Optoelectronical Nanostructures. 4(1) (2019) 51-66.
Available: http://jopn.miau.ac.ir/article_3385.html
[4] M. Akbari Eshkalak, R. Faez, A Computational Study on the Performance of Graphene Nanoribbon Field Effect Transistor, Journal of Optoelectronical Nanostructures, 2(3) (2017) 1-12.
Available: http://jopn.miau.ac.ir/article_2427.html
[5] M. Vadizadeh, G. Darvish, M. Fathipour, A Novel Field Effect Diode (Fed) Structure For Improvement Of Ion/Ioff Ratio Parameter In The Nanometer Regime, IOSR Journal of Electrical and Electronics Engineering. 10. (2015).18-22.
Available: https://www.researchgate.net/publication/299565555_A_Novel_Field_Effect_Diode_Fed_Structure_For_Improvement_Of_I_on_I_off_Ratio_Parameter_In_The_Nanometer_Regime
[6] A. Es-Sakhi, M. Chowdhury, Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. Microelectronics Journal. 62 (2017). 30-37.
Available: https://www.sciencedirect.com/science/article/abs/pii/S0026269217301143
[7] X. Liu, M. Wu, X. Jin, R. Chuai, J Lee. Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures. Journal of computational Electronics. 13(2) (2014) 509–514.
Available: https://link.springer.com/article/10.1007/s10825-014-0562-3
[8] N. Manavizadeh, F. Raissi, E. Soleimani, M. Pourfath. Geometrical study of nanoscale field effect diodes. Semiconductor Science and Technology. 27 (2012). 045011.
Available:https://iopscience.iop.org/article/10.1088/0268-1242/27/4/045011/meta
[9] N. Manavizadeh, F. Raissi, E. Soleimani, M. Pourfath, S. Selberherr. Performance Assessment of Nanoscale Field-Effect Diodes, IEEE Transaction on Electron Devices, vol. 58(8) (2011) 2378-2384.
Available: https://ieeexplore.ieee.org/abstract/document/5779716
[10] M. Vadizadeh, M. Fathipour, G. Darvish. Silicon on Raised Insulator Field
Effect Diode Sori-Fed for Alleviating Scaling Problem in Fed. International Journal of Modern Physics B. 28(5) (2014) 1450038.
Available: https://www.worldscientific.com/doi/abs/10.1142/S0217979214500386
[11] M. Vadizadeh. Dual material gate nanowire field effect diode (DMG-NWFED): Operating principle and properties. Microelectronics Journal. 71 (2018) 1–7.
Available: https://www.sciencedirect.com/science/article/abs/pii/S0026269217305384
[12] B. Touchaei, N. Manavizadeh, Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED. IEEE Transaction on Electron Devices. 64(1) (2016) 306-311.
Available: https://ieeexplore.ieee.org/document/7752852
[13] M. Vadizadeh. Improving gate delay and ION/IOFF in nanoscale heterostructure field effect diode (H-FED) by using heavy doped layers in the channel. Applied Physics A. 122 (2016) 469.
Available: https://link.springer.com/article/10.1007/s00339-016-0009-8
[14] A. Rezaei, B. Azizollah-Ganji, M. Gholipour. Effects of the Channel Length on the Nanoscale Field Effect Diode Performance, Journal of Optoelectronical Nanostructures. 3(2) (2018) 29-40.
Available: http://jopn.miau.ac.ir/article_2862.html
[15] R. Hosseini, M. Fathipour, R. Faez. Quantum simulation study of gate-all-around (GAA) silicon nanowire transistor and double gate metal oxide semiconductor field effect transistor (DG MOSFET). International Journal of the Physical Sciences, 7(28) (2012) 5054-5061.
Available: https://academicjournals.org/journal/IJPS/articleabstract/B27116C16368
[16] A. Ferron, B. Cottle, G. Curatola, G. Fiori, E. Guichard. Schrodinger Approach and Density Gradient Model for Quantum Effects Modeling, A Journal for Process and Device Engineers. 14 (2004) 1-3.
Available: https://www.researchgate.net/publication/268273208_Schrodinger_Approach_and_Density_Gradient_Model_for_Quantum_Effects_Modeling
[17] S. M. Hong, Compact Charge Modeling of Double-Gate MOSFETs Considering the Density-Gradient Equation, Journal of the Electron Device society. 7 (2019). 409-416.
Available: https://ieeexplore.ieee.org/document/8663333
[18] A. Wettstein, A. Schenk, W. Fichtner. Quantum Device-Simulation with the
Density Gradient Model on Unstructured Grids, IEEE Transaction on Electron Devices. 48 (2001) 279-283.
Available: https://ieeexplore.ieee.org/document/902727
[19] A. Brown, A. Martinez, N. Seoane, A. Asenow. Comparison of Density Gradient and NEGF for 3D Simulation of a Nanowire MOSFET, Proceeding of the 2009 Spanish Conference on Electron Devices. (2009) 140-143.
Available: https://ieeexplore.ieee.org/document/4800450
[20] Silvaco Int.: ATLAS User’s Manual, Device simulation Software, Silvaco International, Santa Clara (2016)
[21] A. Schenk. Finite-temperature full random-phase approximation model of band-gap narrowing for silicon device simulation. Journal of Applied Physics. 84 (1998) 3684- 3694.
Available: https://aip.scitation.org/doi/10.1063/1.368545
[22] A. Richter, S.W. Glunz, F. Werner, J. Schmidt, A. Cuevas. Improved quantitative description of Auger Recombination in crystalline silicon. Physical Review B. 86 (2012) 165202.
Available: https://journals.aps.org/prb/abstract/10.1103/PhysRevB.86.165202
[23] W. Shockley, W. Read. Statistics of the Recombination of Holes and Electrons. Physical Review. 87(1952) 835-842.
Available: https://journals.aps.org/pr/abstract/10.1103/PhysRev.87.835
[24] R. N. Hall. Electron Hole Recombination in Germanium. Physical Review. 87(1952) 387.
Available: https://journals.aps.org/pr/abstract/10.1103/PhysRev.87.387