An innovative method for estimating optimal Gate work function and dielectric constant of a nanoscale DG-TFET based on analytical modeling of tunneling length in ambipolar, Off and ON states

Ali Heydari ¹ ( Department of Electrical Engineering, Guilan University, Rasht, Iran. )
Seyed Ali Sedigh Ziabari ² ( Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran )
Fayzollah Khorramrouz ³ ( Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran )

Submited date : 2019-10-23 Accepted date : 2020-04-17

Keywords: 2D Analytical model, Surface potential, BTBT, minimum tunneling length, DG-TFET,

Abstract :

In this paper, we propose an innovative and low computational cost approach that can be used to find optimal values of parameters of a nanoscale dual gate tunneling field-effect transistor (DG-TFET). In this way, after obtaining analytical expressions for potential and energy bands of the device using the Poisson equation, the tunneling length is extracted at source-channel and channel-drain tunnel junctions in the AMBIPOLAR, Off and On states. Due to the tunneling length equation, the different values of gate work function and dielectric constant of the device are swept to determine the minimum and maximum design limits. According to the above range, the necessary checks are made to reach the local optimal behaviors. These optimum points are explained based on the achievement of optimal device performance. The accuracy and consistency of the proposed model is validated with the TCAD simulation results. The present model can be a handful for the study of TFET performance.

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An innovative method for estimating optimal Gate work-function and dielectric constant of a Nano scale DG-TFET based on analytical modeling of tunneling length in ambipolar, Off and ON states

 

Abstract

In this paper, we propose an innovative and low computational cost approach that can be used to find optimal values of parameters of a nanoscale dual gate tunneling field-effect transistor (DG-TFET). In this way, after obtaining analytical expressions for potential and energy bands of the device using the Poisson equation, the tunneling length is extracted at source-channel and channel-drain tunnel junctions in the AMBIPOLAR, Off and On states. Due to the tunneling length equation, the different values of gate work function and dielectric constant of the device are swept to determine the minimum and maximum design limits. According to the above range, the necessary checks are made to reach the local optimal behaviors. These optimum points are explained based on the achievement of optimal device performance. The accuracy and consistency of the proposed model is validated with the TCAD simulation results. The present model can be a handful for the study of TFET performance.

Keywords:  2D Analytical model; Surface potential; BTBT; minimum tunneling length; DG-TFET.

 

1.       Introduction

Scaling of conventional CMOS transistors according to Moore’s law is facing several challenges, such as high OFF-state current, high sub-threshold slope (SS) and other short channel effects (SCEs). The above-mentioned causes poor operation of the device and high power consumption in chips[1–5]. Hence, the proposal of a new device is inevitable. The tunneling field-effect transistor (TFET) is a decent choice because of energy efficiency and lower sub-threshold slope (SS) [6–8]. The major weaknesses of TFETs are low drain current due to poor band to band tunneling rate and conduction in the positive and negative voltages of the gate (ambipolarity).  Several studies have been conducted to overcome these shortcomings that are beyond the scope of this paper [9–14]. One of the main areas of research in the field of semiconductor devices is analytical modeling. Analytical modeling can be useful in the rapid and low-cost evaluation of semiconductor devices. It is also used to offer a model for simulator software [15,16]. Some researchers proposed analytical modeling for TFET using the MOSFET model [17]. Many researchers study the Sub-threshold swing and the threshold voltage of TFET [18,19].

 Several analytical studies try to offer a 2-D or 3-D expression for TFETs with or without considering the impact of the depletion region, mobile charge and drain voltage. Many 2-D studies on TFET modeling analytically calculate the tunneling generation rate using a 2-D electric field and Some studies emphasize the modeling of different physical structures of the device[19–24]. While some other researchers consider device modeling according to the type of insulator and shape and number of gates. Investigating the performance of the TFETs by using the analytical modeling also did not exclude the attention of researchers. Many attempts have focused on analytical modeling of junction-less TFETs [25]. In this paper, we start with the modeling of the surface potential along the channel using a pseudo-2D model [26] considering the depletion regions at source-channel and channel drain junction. We then find the smallest tunneling length which is very essential to finding drain current and in our proposed method. The method presented in this paper is to find the proper values of the work-function of the gate and the dielectric constant with respect to the tunneling length. We derive the tunneling length for AMBIPOLAR, OFF and ON state at different values of the gate work-function and dielectric constant using our proposed method. The two-dimensional curve obtained from this step is analyzed in order to obtain the appropriate values of the parameters. The method of analysis is a combination of qualitative analysis, evaluation of maximum or minimum points of the curves, and also referring to the TCAD simulation results. We believe that this method while avoiding complex optimization procedures is useful in achieving the desired device efficiency. A 2-D dimensional numerical simulation validates accuracy of the proposed model.

 The rest of the paper is organized as follows: In section 2, device structure and analytical modeling of surface potential will be discussed. The tunneling length in AMBIPOLAR, OFF and ON state also will be presented in section 3. The validation of our proposed method also is described in Section 4. Results and discussions and finally the conclusion will be presented in sections 5 and 6 respectively. 

2.       Materials and Methods

Fig. 2 shows a 2-D structure of a dual gate tunneling field-effect transistor (DG-TFET). The total gate length is L2. The silicon body and oxide thicknesses are Tsi and Tox respectively. The Source and the drain are highly doped with p and n-type dopant at a concentration of N1 and N3. The channel region is lightly doped with N2. Regions R1, R2 and R3 demonstrate depletion region at the source side, channel region under the gate and drain side depletion region respectively. L1 and L3 are depletion region length. The other Physical characteristics of the device are listed in Table 1.

2.1.         2-D Poisson’s Equation in the Channel

Neglecting the mobile charge, the 2-D Poisson’s equation in the channel region of the device is given by[27]:

Where demonstrates the 2-D electrostatic potential in the channel, q is the electronic charge,  is the permittivity of silicon and N2 is the channel concentration. The potential distribution along the channel can be approximated by the second-order polynomial as [28–34]:

(1)

Where a0, a1 and a2 are channel length-dependent obtained from properly defined boundary conditions. Using boundary conditions, the surface potential of the channel  can be found as:

(2)

 Where,  and  are oxide capacitance and metal-silicon work-function difference.  Is the silicon work-function as, where  is the electron affinity of the silicon. Substituting (3) in (1) yields the following1-D second orders differential equation:

(3)

Where

(4)

The general and particular solution of (4) is:

(5)

Hence using the potential continuity in the interfaces of two consecutive regions, the coefficients of (6) are:

;

(6)

The interface potential of  and  are derived using the continuity of potential and electric field which will be discussed later.

2.2.        Poisson’s Equation in the Depletion regions

The precise modeling of channel potential involves the consideration of drain and source depletion regions. As is obtained from the TCAD simulation and according to report [35], the major changes in surface potential of region R1 and R2 are along the channel, therefore, we solve the Poisson equation in these regions one-dimensionally. The 1-D Poisson’s equation inside the depletion regions of the device is expressed as:

	(7)
	(8)

Twice integrating the (9)-(10), we get the following expression for  and  given by:

	(9)
	(10)

The extension of the depletion region in the source is as far as the electrostatic potential becomes a constant value of   which is called built-in potential (ψ0). At this point, the electric field will be zero. Meanwhile, the extension of the depletion region in the drain side is as high as the potential reaches the value of   and the electric field becomes zero. (KB is the Boltzmann constant). Using the above-mentioned boundary conditions the other coefficients are as follows:

	(11)
	(12)

And the depletion region length at source and drain side will be derived using the value of the electric field at   and  as:

	(13)
	(14)
	(15)

Solving equations (16)-(17) yields depletion region length as:

	(16)
	(17)

The intermediate potential () can be calculated using the continuity of potential at channel-source and channel-drain interfaces as:

	(18)
	(19)

We find from above-mentioned system of nonlinear equations.

2.3.       Tunneling length 

The tunneling length is the physical path through which the band to band tunneling occurs. This path occurs in the ON, OFF and the AMBIPOLAR state. The difference is in the tunneling region and hence the starting and endpoint. The tunneling length is a path between the two equal potential points. To understand and analyze the tunneling length, we need the energy band diagram in different biasing conditions[36, 37] as: 

	(20)
	(21)

The surface potential of the DG-TFET is shown in Fig. 2(a) for ON, OFF and AMBIPOLAR state. As we expect, an extension of the depletion region at the drain side is more because of higher reverse bias in this side. The lateral electric field is shown in Fig. 2(b). A good agreement between the model and TCAD results is seen.

2.4.        Source-Channel Junction Tunneling length

The energy band diagram of the DG-TFET in the ON state is shown in Fig. 3(a). The closure of the Fermi level with the valence band of the source to the corresponding point in the conduction band of the channel is the minimum tunneling length. However, because of the high level of doping in the source, the difference between the Fermi and valence band can be ignored. Thus, the tunneling starts from the junction of the depletion region with the source and ends in a point in the channel conduction band which the energy value of the start and endpoints of the tunneling is equal. Accordingly, one can write:

,

(22)

Using (8) and xstart= -L1 from (18), the tunneling length in the ON state is expressed as follow:

	(23)
	(24)

2.5.        Channel-Drain Junction Tunneling length 

The energy band alignment between the channel valence band and the drain conduction band is also observed for OFF and Ambipolar state. The energy band diagram in the OFF and the Ambipolar state is shown in Fig. 3(b) and Fig. 3(c) respectively. The tunneling path starts from the channel valence band and ends to drain conduction band. The endpoint is the end of the depletion region extension at the drain side. To achieve the main equation, it is enough to equal the amount of energy at the start and endpoints of the tunneling, as below:

	(25)

Using (6) and (12) one can write:

	(26)
	(27)

 

Where

(28)

The method for calculating the tunneling length in the Ambipolar state is exactly the same as the OFF state because the tunneling phenomenon occurs in the same region (Fig. 3(c).

2.6.       Model validation

The accuracy of the proposed model is verified by comparing the numerical modeling results with 2D numerical simulations. SILVACO ATLAS 2D 5.19.20 R is employed for all simulations. The models used include Shockley Read Hall (SRH) and Auger (AUGER) recombination models, Fermi-Dirac statistics and band-gap narrowing model (BGN) [45–47]. 

3.       Results and discussions

The tunneling length at Source-Channel and Channel-Drain junction at Ambipolar, OFF and ON state is shown in Fig. 3(d). Good consistency between the model and TCAD is observed. After extracting an expression for tunneling length, we assign the different values of the gate work-function and the dielectric constant of the insulator. The result is a three-dimensional graph, which can be used to evaluate the performance of the device. The purpose of this assessment is to reach the optimal local points for the least OFF and Ambipolar current and the highest ON current. It should be noted that the basis of our judgment is the tunneling length in each case. The three-dimensional curves of the tunneling length in the source and drain side junction for various states are shown in Fig. 4. -Fig. 6. The preliminary study of 3D curves can be summarized as follows:

1.       In the Ambipolar state, the tunneling length in the channel-drain junction is maximal when the work-function is equal to 4 eV (Fig. 4(b)). On the other hand, this amount of work-function minimizes the tunneling length at the source side, which is undesirable (Fig. 4(a)). Therefore, the work-function must be selected in such a way that both tunneling lengths are in the optimal position. Therefore, the intermediate values of the work-function, (e.g. 4.2 or 4.3 eV), are suggested.

2.       In the OFF state, tunneling in the source-channel junction is more influenced by the gate work-function than the dielectric constant (Fig. 5(a)). In other words, it is necessary to avoid the lower values of the work-function. At the same time, the lower value of the gate work-function reduces the tunneling length in the channel-drain junction (Fig. 5(b)), which is not at all desirable. Therefore, the higher values of the work-function are preferable. Taking into account simultaneously the realities associated with the tunneling length in the source-channel and channel-drain junction, the higher values of the work-function can be an optimal choice to keep the OFF current down.

3.       In the ON state, the tunneling length in the channel-drain is so high that there is no band to band tunneling in this junction (Fig. 6(b)). In other words, the dielectric constant and the work-function do not interfere in the tunneling of this junction. Meanwhile, the effect of dielectric constant on the source-channel junction tunneling length is more than work-function (Fig. 6(a)). Therefore, selecting high values of dielectric constant reduces the tunneling length and, as a result, increases the drain current (ION).

In order to verify our proposed method, we examine the values of the gate work-function as well as the dielectric constant corresponding to each of the optimal states in the TCAD. The drain current corresponding to each of the above states is shown in Fig. 7. According to the above, high dielectric constant values with any value of work-function can improve the ON current. This is clearly shown in (Fig. 7) for (Wf=4 eV; εr=7) and (Wf=4 eV; εr=21). In these two samples, we have the highest ON current. In the case where the work unction is selected in range 4.2 eV to 4.3 eV, the Ambipolar current is very low. Also, with a work-function equal to 4.5 eV, the minimum OFF current is achievable.

4.       Conclusion

The idea of analytical modeling of DG-TFET can extract a closed-form formula for tunneling length in source-channel and channel-drain junctions. From the perspective of the energy band diagram, surface potential and, lateral electric field, the model corresponds well to the simulation results. To achieve optimal conditions, simultaneous effects of different values of the gate work-function and dielectric constant on the tunneling length in Ambipolar, OFF and ON state have been investigated which has a good agreement with simulation results. Based on the results, the allowable values of the gate work-function and dielectric constant are determined according to the principles of minimum Ambipolar and OFF current and maximum ON current. The simulation results confirm the correctness of this proposal.

 

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Table 1.  Device design and material parameters.

Figures Captions:

Fig. 1. Schematic view of DG-TFET.

Fig. 2. Surface potential of DG-TFET (a) and Lateral electric field (b) for ON state: Vgs=1 V and Vds=1 V; OFF state: Vgs=0 V and Vds=1 V and AMBIPOLAR state: Vgs=-0.5 V and Vds=1 V.

Fig. 3. Source-channel and Channel-Drain tunneling length of DG-TFET for AMBIPOLAR, OFF and ON state (a); Energy band diagram in the ON state (b); OFF state (c) and AMBIPOLAR state (d).

Fig. 4. The effect of dielectric constant and gate work-function on tunneling length of Source-Channel junction (a) and Channel-Drain junction (b) in the AMBIPOLAR state ( Vds=1 V and Vgs=-0.5 V).

Fig. 5. The effect of dielectric constant and gate work-function on tunneling length of Source-Channel junction (a) and Channel-Drain junction (b) in the OFF state ( Vds=1 V and Vgs= 0 V).

Fig. 6. The effect of dielectric constant and gate work-function on tunneling length of Source-Channel junction (a) and Channel-Drain junction (b) in the ON state ( Vds=1 V and Vgs=1 V).

Fig. 7. Drain current of DG-TFET extracted from our model and SILVACO TCAD simulation tool.

  

Table 1

(29)

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