معرفی یک D Flip-Flop مبتکرانه برای طراحی ثبات چهار ارزشی QCA
محورهای موضوعی : انرژی های تجدیدپذیر
علیرضا نویدی
1
,
رضا صباغی ندوشن
2
,
مسعود دوستی
3
1 - دانشکده مهندسی برق و کامپیوتر- واحد علوم و تحقیقات، دانشگاه آزاد اسلامی، تهران، ایران
2 - دانشکده مهندسی برق- واحد تهران مرکزی، دانشگاه آزاد اسلامی، تهران، ایران
3 - دانشکده مهندسی برق و کامپیوتر- واحد علوم و تحقیقات، دانشگاه آزاد اسلامی، تهران، ایران
کلید واژه: اتوماتای سلولی نقاط کوانتومی چهار ارزشی (QQCA), منطق چهارچهاری, فلیپ فلاپ D چهارچهاری, ثبات چهارچهاری, QCASim,
چکیده مقاله :
اتوماتای سلولی نقاط کوانتومی (QCA) با بهره‌گیری از پیشرفت‌های فن‌آوری نانو، بسیاری از محدودیت‌هایی که نیمه‌رسانا اکسید فلزی مکمل (CMOS) با آن روبرو شده بود را برطرف کرده است. مشخصه‌های نامطلوب همانند جریان‌های نشتی زیاد، طراحی‌های CMOS را در ابعاد نانو محدود می‌سازد. ایده‌ی طراحی سیستم‌های چند ارزشی منطقی (MVL) به جای دودویی استاندارد، برای بسیاری از طراحان جذاب شده است. کاربرد MVL در طراحی مدارهای دیجیتال، مزایای بسیاری نسبت به روش‌های مرسوم دارد. فلیپ فلاپ D یک مدار ترتیبی عمده در هر ثباتی است. در این مقاله، یک فلاپ فلاپ D چهار ارزشی مبتنی بر اتوماتای سلولی نقاط کوانتومی چهارچهاری (QQCA) معرفی شده و ساختار مدل چهارچهاری پیشنهادی شرح داده شده است. همچنین ما با استفاده از فلیپ فلاپ D چهارچهاری ارائه شده، یک ثبات 4 کوبیتی پیشنهاد کرده‌ایم. هر دو مدار توسط QCASim (نسخه چهارچهاری)، شبیه‌سازی و ارزیابی شده‌اند. QCASim می‌تواند نتیجه‌ی شبیه‌سازی را در قالب شکل موج و جدول صحت نمایش دهد. کار ما با سایر آثار منتشر شده مورد مقایسه قرار گرفته است. نتایج شبیه‌سازی نشان می‌دهد که مدار پیشنهادی از نظر تاخیر و مصرف انرژی کارآمد است.
Taking advantage of advances in Nanotechnology, the quantum-dot cellular automata (QCA) has overcome many limitations that complementary metal-oxide-semiconductor (CMOS) had been confronted. Undesirable characteristics such as too many leakage currents limit the CMOS designs in nano dimensions. The idea of designing multiple-valued logic (MVL) systems rather than standard binary has gotten attractive to many designers. The application of MVL in the design of digital circuits offers so many advantages over traditional methods. D flip-flop is a primary sequential circuit in any register. In this paper, a novel quaternary D flip-flop based on introducing quaternary QCA (QQCA) is presented. The structure of our quaternary model is clarified. Also, we have proposed a 4-qubits register by utilizing the presented quaternary D flip-flop. Both circuits got simulated and evaluated by QCASim (quaternary edition). QCASim can illustrate the simulation result in a truth table and a waveform format. Our work got compared with other published works. The simulation results show that our proposed circuit is efficient in terms of latency and energy consumption.
[1] S.M.A. Zanjani, M. Parvizi, "Design and simulation of a bulk driven operational trans-conductance amplifier based on CNTFET technology", Journal of Intelligent Procedures in Electrical Technology, vol. 12, no. 45, pp. 65-76, June 2021 (in Persian) (dor: 20.1001.1.23223871.1400.12.1.5.1).
[2] A. Baghi-Rahin, V. Baghi-Rahin, "A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders", Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 13-22, 2019 (in Persian).
[3] F. Peng, Y. Zhang, R. Kuang, G. Xie, "Spars: a full flow quantum-dot cellular automata circuit design tool", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 68, no. 4, pp. 1233-1237, April 2021 (doi: 10.1109/TCSII.2020.3039532).
[4] E. Blair, "Electric-field inputs for molecular quantum-dot cellular automata circuits", IEEE Trans. on Nanotechnology, vol. 18, pp. 453-460, April 2019 (doi: 10.1109/TNANO.2019.2910823).
[5] V. Levashenko, I. Lukyanchuk, E. Zaitseva, M. Kvassay, J. Rabcan, P. Rusnak, "Development of programmable logic array for multiple-valued logic functions", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 4854-4866, Dec. 2020 (doi: 10.1109/TCAD.2020.2966676).
[6] A. Norouzi Doshanlou, M. Haghparast, M. Hosseinzadeh, M. Reshadi, "Efficient design of quaternary quantum comparator with only a single ancillary input", IET Circuits, Devices and Systems, vol. 14, no. 1, pp. 80-87, Jan. 2020 (doi: 10.1049/iet-cds.2019.0098).
[7] F. Sharifi, A. Panahi, H. Sharifi, K. Navi, N. Bagherzadeh, H. Thapliyal, "Design of quaternary 4–2 and 5–2 compressors for nanotechnology", Journal of Computers and Electrical Engineering, vol. 56, pp. 64-74. Nov. 2016 (doi: 10.1016/j.compeleceng.2016.11.006).
[8] E. Abiri, A. Darabi, S. Salem, "Design of multiple-valued logic gates using gate-diffusion input for image processing applications", Computers and Electrical Engineering, vol. 69, pp. 142–157, July 2018 (doi: 10.1016/j.compeleceng.2018.05.019).
[9] A. Navidi, R. Sabbaghi-Nadooshan, M. Dousti, "TQCAsim: an accurate design and essential simulation tool for ternary logic quantum-dot cellular automata", Scientia Iranica, in Press, 2021 (doi: 10.24200/SCI.2021.53471.3256).
[10] S.M. Mohaghegh, R. Sabbaghi-Nadooshan, M. Mohammadi, "Designing ternary quantum-dot cellular automata logic circuits based upon an alternative model", Computers and Electrical Engineering, vol. 71, pp. 43–59, Oct. 2018 (doi: 10.1016/j.compeleceng.2018.07.001).
[11] SM. Mohaghegh, R. Sabbaghi-Nadooshan, M. Mohammadi, "Design of a ternary QCA multiplier and multiplexer: a model-based approach", Analog Integrated Circuits and Signal Processing, vol. 101, pp. 23–29, May 2019 (doi: 10.1007/s10470-019-01465-3).
[12] SM. Mohaghegh, R. Sabbaghi-Nadooshan, M. Mohammadi, "Innovative model for ternary QCA gates", IET Circuits, Devices & Systems, vol. 12, no. 2, pp. 189–195, Mar. 2018 (doi: 10.1049/iet-cds.2017.0276).
[13] T.F. Cesar, L.F.M. Vieira, M.A.M. Vieira, O.P. Vilela Neto, "Cellular automata-based byte error correction in QCA", Nano Communication Networks, vol. 23, Article Number: 100278, Feb. 2020 (doi: 10.1016/j.nancom.2019.100278).
[14] V. Vankamamidi, M. Ottavi, F. Lombardi, "Clocking and cell placement for QCA", Proceeding of the IEEE/NANO, pp. 343-346, OH, USA, July 2006 (doi: 10.1109/NANO.2006.247647).
[15] M. Morris Mano, M. D. Ciletti, "Digital Design", 6th Edition, Pearson, 2018.
[16] I. Jahangir, A. Das, M. Hasan, "Design of novel quaternary encoders and decoders", Proceeding of the IEEE/ICIEV, pp. 1021-1026, Dhaka, May 2012 (doi: 10.1109/ICIEV.2012.6317530).
[17] M. A. Dehkordi, M. Sadeghi, "A new approach to design D-ff in QCA technology", Proceedings of the IEEE/ICCSNT, pp. 2245-2248, Changchun, China, Dec. 2012 (doi: 10.1109/ICCSNT.2012.6526365).
[18] T. N. Sasamal, A. K. Singh, U. Ghanekar, "Design and implementation of QCA D-flip-flops and RAM cell using majority gates", Journal of Circuits, Systems and Computers, vol. 28, no. 05, May 2019 (doi: 10.1142/S0218126619500798).
[19] H. Alamdar, G. Ardeshir, M. Gholami, "Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal", International Nano Letters, vol. 10, pp. 111-118, June 2020 (doi: 10.1007/s40089-020-00300-2).
[20] S. Senthilnathan, S. Kumaravel, "Power-efficient implementation of pseudo-random number generator using quantum dot cellular automata-based D flip flop", Computers and Electrical Engineering, vol. 85, Article Number: 106658, July 2020 (doi: 10.1016/j.compeleceng.2020.106658).
[21] J.C. Jeon, "Low-complexity QCA universal shift register design using multiplexer and D flip-flop based on electronic correlations", The Journal of Supercomputing, vol. 76, pp. 6438–6452, Aug. 2020 (doi: 10.1007/s11227-019-02962-y).
[22] M. G. Roshan, M. Gholami, "Novel D Latches and D flip-flops with set and reset ability in QCA nanotechnology using minimum cells and area", International Journal of Theoretical Physics, vol. 57, pp. 3223–3241, Oct. 2018 (doi: 10.1007/s10773-018-3840-1).
[23] Z. Song, G. Xie, X. Cheng, L. Wang, Y. Zhang, "An ultra-low cost multilayer RAM in quantum-dot cellular automata", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3397-3401, Dec. 2020 (doi: 10.1109/TCSII.2020.2988046).
[24] W. Haixia, Z. Shunan, S. Zhentao, Q. Xiaonan, C. Yueyang, "Design of low-power quaternary flip-flop based on dynamic source-coupled logic", Proceedings of the IEEE/ICECC, pp. 826-828, Ningbo, China, Sep. 2011 (doi: 10.1109/ICECC.2011.6066389).
[25] S. Shim, S. Park, S. Hong, "Design of Q-IDEN D flip-flop using RS latch", International Journal of Computer Sceince and Network Security, vol. 6, no. 9A, Sept. 2006.
[26] G.S. Na, Y.H. Choi, "Quaternary D flip-flop with advanced performance", The Institute of Electronics and Information Engineers, vol. 44, no. 2, pp. 14-20, 2007.
[27] H. Wu, Y. Bai, X. Li, Y. Wang, "Design of high-speed quaternary D flip-flop based on multiple-valued current-mode", Journal of Physics: Conference Series, vol. 1626, June 2020.
[28] A. Mochizuki, T. Kitamura, H. Shirahama, T. Hanyu, "Design of a microprocessor datapath using four-valued differential-pair circuits", Proceedings of the IEEE/ISMVL, pp. 14-14, Singapore, May 2006 (doi: 10.1109/ISMVL.2006.18).
[29] H. Shirahama, T. Hanyu, "Design of high-performance quaternary adders based on output-generator sharing", Proceedings of the IEEE/ISMV, pp. 8-13, Dallas, USA, May 2008 (doi: 10.1109/ISMVL.2008.11).
[30] A. Navidi, R. Sabbaghi-Nadooshan, M. Dousti, "A creative concept for designing and simulating quaternary logic gates in quantum-dot cellular automata", Frontiers of Information Technology and Electronic Engineering, in Press, 2021 (doi: 10.1631/FITEE.2000590).
[31] K. Walus, T. J. Dysart, G. A. Jullien, R. A. Budiman, "QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata", IEEE Trans. on Nanotechnology, vol. 3, no. 1, pp. 26-31, Mar. 2004 (doi: 10.1109/TNANO.2003.820815).
[32] https://qcasim.com, https://bit.ly/3nFqdTj, 2020.
[33] P. Pain, A. Sadhu, K. Das, M. R. Kanjilal, "Physical proof and simulation of ternary logic gate in ternary quantum dot cellular automata", Computational Advancement in Communication Circuits and Systems, Lecture Notes in Electrical Engineering, vol. 575, pp. 375-385, 2020 (doi: 10.1007/978-981-13-8687-9_34).
[34] B. K. Bhoi, N. K. Misra, I. Dash, A. Patra, "A redundant adder architecture in ternary quantum-dot cellular automata", Smart Intelligent Computing and Applications, vol. 159, pp. 375-384, 2020 (doi: 10.1007/978-981-13-9282-5_35).
[35] S. Srivastava, S. Sarkar, S. Bhanja, "Estimation of upper bound of power dissipation in QCA circuits", IEEE Trans. on Nanotechnology, vol. 8, no. 1, pp. 116-127, Jan. 2009 (doi: 10.1109/TNANO.2008.2005408).
_||_[1] S.M.A. Zanjani, M. Parvizi, "Design and simulation of a bulk driven operational trans-conductance amplifier based on CNTFET technology", Journal of Intelligent Procedures in Electrical Technology, vol. 12, no. 45, pp. 65-76, June 2021 (in Persian) (dor: 20.1001.1.23223871.1400.12.1.5.1).
[2] A. Baghi-Rahin, V. Baghi-Rahin, "A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders", Journal of Intelligent Procedures in Electrical Technology, vol. 10, no. 37, pp. 13-22, 2019 (in Persian).
[3] F. Peng, Y. Zhang, R. Kuang, G. Xie, "Spars: a full flow quantum-dot cellular automata circuit design tool", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 68, no. 4, pp. 1233-1237, April 2021 (doi: 10.1109/TCSII.2020.3039532).
[4] E. Blair, "Electric-field inputs for molecular quantum-dot cellular automata circuits", IEEE Trans. on Nanotechnology, vol. 18, pp. 453-460, April 2019 (doi: 10.1109/TNANO.2019.2910823).
[5] V. Levashenko, I. Lukyanchuk, E. Zaitseva, M. Kvassay, J. Rabcan, P. Rusnak, "Development of programmable logic array for multiple-valued logic functions", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 4854-4866, Dec. 2020 (doi: 10.1109/TCAD.2020.2966676).
[6] A. Norouzi Doshanlou, M. Haghparast, M. Hosseinzadeh, M. Reshadi, "Efficient design of quaternary quantum comparator with only a single ancillary input", IET Circuits, Devices and Systems, vol. 14, no. 1, pp. 80-87, Jan. 2020 (doi: 10.1049/iet-cds.2019.0098).
[7] F. Sharifi, A. Panahi, H. Sharifi, K. Navi, N. Bagherzadeh, H. Thapliyal, "Design of quaternary 4–2 and 5–2 compressors for nanotechnology", Journal of Computers and Electrical Engineering, vol. 56, pp. 64-74. Nov. 2016 (doi: 10.1016/j.compeleceng.2016.11.006).
[8] E. Abiri, A. Darabi, S. Salem, "Design of multiple-valued logic gates using gate-diffusion input for image processing applications", Computers and Electrical Engineering, vol. 69, pp. 142–157, July 2018 (doi: 10.1016/j.compeleceng.2018.05.019).
[9] A. Navidi, R. Sabbaghi-Nadooshan, M. Dousti, "TQCAsim: an accurate design and essential simulation tool for ternary logic quantum-dot cellular automata", Scientia Iranica, in Press, 2021 (doi: 10.24200/SCI.2021.53471.3256).
[10] S.M. Mohaghegh, R. Sabbaghi-Nadooshan, M. Mohammadi, "Designing ternary quantum-dot cellular automata logic circuits based upon an alternative model", Computers and Electrical Engineering, vol. 71, pp. 43–59, Oct. 2018 (doi: 10.1016/j.compeleceng.2018.07.001).
[11] SM. Mohaghegh, R. Sabbaghi-Nadooshan, M. Mohammadi, "Design of a ternary QCA multiplier and multiplexer: a model-based approach", Analog Integrated Circuits and Signal Processing, vol. 101, pp. 23–29, May 2019 (doi: 10.1007/s10470-019-01465-3).
[12] SM. Mohaghegh, R. Sabbaghi-Nadooshan, M. Mohammadi, "Innovative model for ternary QCA gates", IET Circuits, Devices & Systems, vol. 12, no. 2, pp. 189–195, Mar. 2018 (doi: 10.1049/iet-cds.2017.0276).
[13] T.F. Cesar, L.F.M. Vieira, M.A.M. Vieira, O.P. Vilela Neto, "Cellular automata-based byte error correction in QCA", Nano Communication Networks, vol. 23, Article Number: 100278, Feb. 2020 (doi: 10.1016/j.nancom.2019.100278).
[14] V. Vankamamidi, M. Ottavi, F. Lombardi, "Clocking and cell placement for QCA", Proceeding of the IEEE/NANO, pp. 343-346, OH, USA, July 2006 (doi: 10.1109/NANO.2006.247647).
[15] M. Morris Mano, M. D. Ciletti, "Digital Design", 6th Edition, Pearson, 2018.
[16] I. Jahangir, A. Das, M. Hasan, "Design of novel quaternary encoders and decoders", Proceeding of the IEEE/ICIEV, pp. 1021-1026, Dhaka, May 2012 (doi: 10.1109/ICIEV.2012.6317530).
[17] M. A. Dehkordi, M. Sadeghi, "A new approach to design D-ff in QCA technology", Proceedings of the IEEE/ICCSNT, pp. 2245-2248, Changchun, China, Dec. 2012 (doi: 10.1109/ICCSNT.2012.6526365).
[18] T. N. Sasamal, A. K. Singh, U. Ghanekar, "Design and implementation of QCA D-flip-flops and RAM cell using majority gates", Journal of Circuits, Systems and Computers, vol. 28, no. 05, May 2019 (doi: 10.1142/S0218126619500798).
[19] H. Alamdar, G. Ardeshir, M. Gholami, "Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal", International Nano Letters, vol. 10, pp. 111-118, June 2020 (doi: 10.1007/s40089-020-00300-2).
[20] S. Senthilnathan, S. Kumaravel, "Power-efficient implementation of pseudo-random number generator using quantum dot cellular automata-based D flip flop", Computers and Electrical Engineering, vol. 85, Article Number: 106658, July 2020 (doi: 10.1016/j.compeleceng.2020.106658).
[21] J.C. Jeon, "Low-complexity QCA universal shift register design using multiplexer and D flip-flop based on electronic correlations", The Journal of Supercomputing, vol. 76, pp. 6438–6452, Aug. 2020 (doi: 10.1007/s11227-019-02962-y).
[22] M. G. Roshan, M. Gholami, "Novel D Latches and D flip-flops with set and reset ability in QCA nanotechnology using minimum cells and area", International Journal of Theoretical Physics, vol. 57, pp. 3223–3241, Oct. 2018 (doi: 10.1007/s10773-018-3840-1).
[23] Z. Song, G. Xie, X. Cheng, L. Wang, Y. Zhang, "An ultra-low cost multilayer RAM in quantum-dot cellular automata", IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3397-3401, Dec. 2020 (doi: 10.1109/TCSII.2020.2988046).
[24] W. Haixia, Z. Shunan, S. Zhentao, Q. Xiaonan, C. Yueyang, "Design of low-power quaternary flip-flop based on dynamic source-coupled logic", Proceedings of the IEEE/ICECC, pp. 826-828, Ningbo, China, Sep. 2011 (doi: 10.1109/ICECC.2011.6066389).
[25] S. Shim, S. Park, S. Hong, "Design of Q-IDEN D flip-flop using RS latch", International Journal of Computer Sceince and Network Security, vol. 6, no. 9A, Sept. 2006.
[26] G.S. Na, Y.H. Choi, "Quaternary D flip-flop with advanced performance", The Institute of Electronics and Information Engineers, vol. 44, no. 2, pp. 14-20, 2007.
[27] H. Wu, Y. Bai, X. Li, Y. Wang, "Design of high-speed quaternary D flip-flop based on multiple-valued current-mode", Journal of Physics: Conference Series, vol. 1626, June 2020.
[28] A. Mochizuki, T. Kitamura, H. Shirahama, T. Hanyu, "Design of a microprocessor datapath using four-valued differential-pair circuits", Proceedings of the IEEE/ISMVL, pp. 14-14, Singapore, May 2006 (doi: 10.1109/ISMVL.2006.18).
[29] H. Shirahama, T. Hanyu, "Design of high-performance quaternary adders based on output-generator sharing", Proceedings of the IEEE/ISMV, pp. 8-13, Dallas, USA, May 2008 (doi: 10.1109/ISMVL.2008.11).
[30] A. Navidi, R. Sabbaghi-Nadooshan, M. Dousti, "A creative concept for designing and simulating quaternary logic gates in quantum-dot cellular automata", Frontiers of Information Technology and Electronic Engineering, in Press, 2021 (doi: 10.1631/FITEE.2000590).
[31] K. Walus, T. J. Dysart, G. A. Jullien, R. A. Budiman, "QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata", IEEE Trans. on Nanotechnology, vol. 3, no. 1, pp. 26-31, Mar. 2004 (doi: 10.1109/TNANO.2003.820815).
[32] https://qcasim.com, https://bit.ly/3nFqdTj, 2020.
[33] P. Pain, A. Sadhu, K. Das, M. R. Kanjilal, "Physical proof and simulation of ternary logic gate in ternary quantum dot cellular automata", Computational Advancement in Communication Circuits and Systems, Lecture Notes in Electrical Engineering, vol. 575, pp. 375-385, 2020 (doi: 10.1007/978-981-13-8687-9_34).
[34] B. K. Bhoi, N. K. Misra, I. Dash, A. Patra, "A redundant adder architecture in ternary quantum-dot cellular automata", Smart Intelligent Computing and Applications, vol. 159, pp. 375-384, 2020 (doi: 10.1007/978-981-13-9282-5_35).
[35] S. Srivastava, S. Sarkar, S. Bhanja, "Estimation of upper bound of power dissipation in QCA circuits", IEEE Trans. on Nanotechnology, vol. 8, no. 1, pp. 116-127, Jan. 2009 (doi: 10.1109/TNANO.2008.2005408).