Exploring the VLIW Architecture Space for Network Applications

Subject Areas : Journal of Computer & Robotics

Mostafa  E. Salehi ¹ (Islamic Azad University, Qazvin Branch, Qazvin, Iran)
Ali  Torabi ² (Islamic Azad University, Qazvin Branch, Qazvin, Iran)
Abolfazl  Salarian ³ (Islamic Azad University, Qazvin Branch, Qazvin, Iran)

Received: 2009-09-23 Accepted : 2010-01-22 Published : 2012-06-12

Keywords: Design Space Exploration, VLIW Architecture, Packet-processing Applications,

Abstract :

The increasing diversity in packet-processing applications together with the rapid increase in channel bandwidth has brought about greater complexity in communication protocols. Also influenced by these factors is the computational load for packet-processing engines, demanding high performance microprocessor designs as an indispensable solution. This paper reports on extensive simulation experiments carried out for exploring the performance of instruction-level parallel Very Long Instruction Word (VLIW) processors executing packet-processing applications. On the grounds of the experimental results, a design space exploration has been used to derive an efficient application-specific VLIW processor architecture based on the VEX instruction set architecture. The VEX simulator toolset has been used for design space exploration, and a number of networking applications have been chosen to serve in guiding the architectural exploration. The optimization measures achieve up to 60% improvement in performance for the most representative packet-processing applications.

References:

[1] B. Klein and J. Garza, Agere systems – communications optimized payload plus network processor architecture, in Network Processor Design: Issues and Practices. Morgan Kaufmann, San Francisco, California, vol. 1, pp. 219–233, 2002.
[2] J. Marshall, Cisco systems – Toaster2, in network processor design: issues and practices. Morgan Kaufmann, San Francisco, California, vol. 1, pp. 235–248, 2002.
[3] P. Lekkas, Network processors architectures, Protocols and Platforms, McGraw Hill, 2003.
[4] B. Khailany, W. J. Dally, et al., Imagine: Media processing with streams, IEEE Micro, pp. 35–46, March/April 2001.
[5] Tensilica - Tensilica: Customizable Processor Cores for the Dataplane, Available online: http://www.tensilica.com/
[6] R. R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung, and M. McCloud, Rapid VLIW processor customization for signal processing applications using combinational hardware functions, EURASIP Journal on Applied Signal Processing, article ID. 46472, pp. 1-23, 2006.
[7] G. Ascia, V. Catania, M. Palesi, D. Patti, Multi-objective optimization of a parameterized VLIW architecture, In. Proc. of the NASA/DoD Conf. on Evolution Hardware, 2004.
[8] E. Salami, M. Valero, Initial evaluation of multimedia extensions on VLIW architectures, SAMOS 2004, LNCS 3133, pp. 403-412, 2004.
[9] A. K. Jones, R. Hoare, D. Kusic, An FPGA-based VLIW processor with custom hardware execution, In Proc. of FPGA’05, pp. 107-117, February 2005.
[10] D.byo Saptono, V. Brost, F. Yang, and E. Prasetyo, Design space exploration for a custom VLIW architecture: direct photo printer hardware setting using VEX compiler, In Proc. of IEEE Int. Conf. on Signal Image Technology and Internet Based Systems, pp. 416-421, 2008.
[11] J. A. Fisher, P. Faraboschi, C. Young, Embedded computing a VLIW approach to architecture, Compilers and Tools, Elsevier Inc, 2005.
[12] Hewlett-Packard Laboratories. Vex toolchain. http://www.hpl.hp. com/downloads/vex.
[13] P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homewood, Lx: A technology platform for customizable VLIW embedded processing, In 27th Int. Symp. on Computer Architecture (ISCA), pages 203-213, 2000.
[14] IETF Available from: http://www.ietf.org/
[15] T. Wolf and M. A. Franklin, CommBench a telecommunications benchmark for network processors, in proc. of IEEE Int. Symp. on Performance Analysis of Systems and Software (ISPASS), pp. 154-162, April 2000,.
[16] G. Memik, W. H. Mangione-Smith, and W. Hu, NetBench: A benchmarking suite for network processors, in Proc. Of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 39-42, November 2001.
[17] B. K. Lee and L. K. John, NpBench: A benchmark suite for control plane and data plane applications for network processors, in proc. of IEEE Int. Conf. on Computer Design (ICCD 03), pp. 226-233, October 2003.
[18] R. Ramaswamy and T. Wolf, PacketBench: A tool for workload characterization of network processing, in proc. of IEEE Int. Workshop on Workload Characterization, pp. 42-50, October 2003.
[19] EEMBC, The embedded microprocessor benchmark consortium, Available from: http://www.eembc.org/home.php.
[20] F. Baker. Requirements for IP version 4 routers. RFC 1812, Network Working Group, June 1995.
[21] S. Kent and R. Atkinson. Security architecture for the internet protocol. RFC 2401, Network Working Group, November 1998.