Using Chip Master Planning in Automatic ASIC Design Flow to Improve Performance and Buffer Resource Management

Subject Areas : Journal of Computer & Robotics

Ali  Jahanian ¹ (Department of Electrical and Computer Engineering, Shahid Beheshti University, G. C., Tehran, Iran)
Morteza  Saheb Zamani ² (IT and Computer Engineering Department, Amirkabir University of Technology, Tehran, Iran)

Received: 2009-10-11 Accepted : 2010-03-13 Published : 2012-06-12

Keywords: Routability, Planning, Placement,

Abstract :

Modern integrated circuits consist of millions of standard cells and routing paths. In nano-scale designs, mis-prediction is a dominant problem that may diminish the quality of physical design algorithms or even result in the disruption of the convergence of the design cycle. In this paper, a new planning methodology is presented in which a master-plan of the chip is constructed at the early levels of the physical design, preparing for the operation of the subsequent physical design stages. As a proof of concept study, the proposed planning design flow is applied to both wire planning and buffer resource planning, and the outcomes are compared against conventional contributions. Experimental results reveal considerable improvements in terms of performance, timing yield and buffer usage.

References:

[1] H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, and N. Sherwani, Integrated floorplanning and interconnect planning, In Proc. of Int. Conf. on Computer Aided Design, pp.354-357, 1999.
Table 4
Experimental results for the conventional buffer insertion flow and BMPBI flow Circuit WSR Conventional buffer insertion flow BMP-based buffer insertion flow (BMPBI) PDP Reduction CPU Time Overhead #buffs Delay (ps) PDP Avg. PDP CPU time (sec) #buffs Delay (ps) PDP Avg. PDP CPU time (sec) des_area 15% 27 1598 23298.84 17716.3 5.1 14 1587 11997.72 15232.92 5.3 1.4% 3% 10% 19 1578 16190.28 13 1602 11246.04 3% 16 1581 13659.84 26 1600 22464 systemaes 15% 10 2203 11896.2 13060.7 10.7 9 2230 10837.8 10597.32 11.1 2.3% 3% 10% 14 2193 16579.08 9 2203 10706.58 3% 9 2203 10706.58 9 2203 10706.58 tv80 15% 39 2364 49764.8 46312.1 11 22 2366 28108 42096.4 11.4 9.1% 3% 10% 41 2355 52135.7 24 2365 37035.9 3% 29 2365 37035.9 48 2359 61145.3 ac97_ctrl 15% 11 823 4888.6 3780.8 14 7 834 3152.5 3477.5 14.5 8.02% 3% 10% 6 825 2673 9 819 3980 3% 7 FAILED - 4 825 3300 dma 15% 133 2667 191543.9 192498.9 26.3 127 2706 185577.4 166114.66 27 13.7% 5.7% 10% 138 2596 193454 99 2712 144983.5 3% 263 FAILED - 119 2611 167782.8 aes_core 15% 18 1400 25200 31711.3 20.3 19 1390 26410 20496.66 21.7 35% 5.5% 10% 19 1390 26410 22 1340 29480 3% 31 1404 43524 4 1400 5600 Average 11.58% 3.86%
Journal of Computer & Robotics 1 (2010) 125-135
135
[2] J. Cong and D. pan, Wire width planning for interconnect performance optimization, In IEEE Trans. on Computer Aided Design, Vol.21, No.3, pp.319-329, March 2002. [3] R. Lu and C.K. Koh, Interconnect planning with local area constrained retiming, In Proc. of Design Automation and Test in Europe, pp.442-447, 2003. [4] J. Cong, T. Kong, and D. Pan, Buffer block planning for interconnect planning and prediction, In IEEE Trans. on VLSI, Vol.9, No.6, pp.929-937, 2001. [5] C.W. Sham and E.F.Y. Young, Routability driven floorplanner with buffer block planning, In Proc. of Int. Symposium on Physical Design, pp.470-480, 2002. [6] I. H. Jiang, Y.W. Chang, J.Y Jou, and K.Y. Chao, Simultaneous floorplan and buffer-block optimization, In IEEE Trans. on Computer Aided Design, Vol.23, No.5, 2004. [7] Y. Ma, X. Hong, S. Dong, S. Chen, C.K.Cheng, J. Gu, Buffer planning as an integral part of floorplanning with consideration of routing congestion, In IEEE Trans. on Computer Aided Design, Vol.24, No.4, 2005. [8] C.J. Alpert, H. Jiang, S.S. Sapatnekar, and p.G. Villarrubia, A practical methodology for early buffer and wire resource allocation, In IEEE Trans. on Computer Aided Design, Vol.22, No.5, pp. 573–583, 2003. [9] D. Hill and A.B. Kahng, RTL to GDSII-From foilware to standard practice, In IEEE Design and Test of Computers, pp.9-12, 2004.
[10] A. Madanipour, Social exclusion in european cities: processes, experiences and responses, regional development and public policy series, Routledge Pub., London, 2003.
[11] R. Hameed and O. Nadeem, Challenges of implementing urban master plans: the lahore experience, In Proc. of World Academy of Science Engineering and Technology, Vol. 17, pp. 335-342, 2006. [12] J.A. Roy, et al, Capo: robust and scalable open-source min-cut floorplacer, In Proc. of Int. Symposium on Physical Design, pp.224-226, 2005.
[13] A. jahanian and M. Saheb Zamani, Improved timing closure by early buffer planning in floor-placement design flow, In Proc. of IEEE/ACM Great Lakes Symposium on VLSI, pp. 558-563, 2007. [14] A. Jahanian and M. Saheb Zamani, Performance and timing yield enhancement using Highway-on-Chip Planning, In Proc. of EuroMicro Digital System Design, Italy, 2008. [15] N. Sherwani, Algorithms for VLSI physical design automation, 3rd edition, Kluwer Academic Publishers, Boston, MA, 1999. [16] IWLS Benchmarks , Available on http://iwls.org/iwls2005/ benchmarks.html, 2005.
[17] Magma design automation, a complete design solution for structured ASICs, Available on http://www.magma-da.com, 2005. [18] Y. Matsumoto, M. Hioki, T. Kawanami, and T. Tsutsumi, Performance and yield enhancement of FPGAs with within-die variation using multiple configurations, In Proc. of Int. Symposium on FPGAs, pp.169-177, 2007.
[19] H. Chen, C. Qiao, F. Zhou, and C. K. Cheng, Refined single trunk tree: a rectilinear Steiner tree generator for interconnect prediction, In Proc. of System Level Interconnect Prediction Conf., pp. 85-89, 2002.