یک مدل جدید برای افزایش کارایی در شبکه روی تراشه نوری بر اساس الگوریتم مسیریابی تطبیقی
محورهای موضوعی : شبکه های کامپیوتری و امنیت
محمدرضا همتی
1
,
سیدمحمدعلی زنجانی
2
,
الهام یعقوبی
3
1 - دانشکده مهندسی کامپیوتر، واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران
2 - دانشکده مهندسی برق، واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران
3 - دانشکده مهندسی کامپیوتر، واحد نجف‌آباد، دانشگاه آزاد اسلامی، نجف‌آباد، ایران
کلید واژه: الگوریتم تحمل‌پذیر خطا, مسیریابی پویای آگاه از ازدحام, شبکه روی تراشه, الگوریتم مسیریابی تطبیقی,
چکیده مقاله :
توانمصرفی کمتر، پهنای باند ارتباطی بزرگ‌تر و تأخیر کمتر از مزایای شبکه های نوری نسبت به ارتباطات الکتریکی است؛ اما چالش هایی مانند مسیریابی و هم‌بندی در این شبکه ها وجود دارد به نحوی‌که برای ارسال داده، نیاز به پیمودن گام های زیادی است که باعث بزرگ‌تر شدن شبکه و اتلاف می شود. با پیچیده تر شدن و بزرگ‌تر شدن شبکه ها، در ساخت شبکه روی تراشه، مشکلاتی نظیر هزینه ارتباطات بین اجزاء و احتمال بروز هر خرابی غیر قابل پیش‌بینی در مدارهای ارتباطی وجود دارد. از این رو ارائه یک الگوریتم تحمل پذیر خطا، نقش مهمی در گسترش معماری شبکه روی تراشه دارد. در این مقاله، یک الگوریتم مسیریابی تطبیقی تحمل پذیر اشکال ارائه خواهد شد که هدف اصلی آن، ایجاد توانایی جهت تعامل با تعداد قابل قبولی اِشکال بدون از کار انداختن گره های سالم در شبکه است. نتایج حاصل از شبیه سازی تأخیر پیام در روش پیشنهادی، برابر با 5- ۱۰× 1 و گرادیان برابر 5- ۱۰× 169/1 به ازای epotch مساوی با 280 است که توانایی آن را در کاهش تأخیر بر روی شبکه اثبات می نماید. تغییر بسیار جزئی تأخیر پیام در ارزیابی روش پیشنهادی، نیز نشانگر قابل قبول بودن روش پیشنهادی است. همچنین، وجود برابر با 7- ۱۰× 1 و گرادیان برابر 3- ۱۰× 527/1 به ازای epotch مساوی با 350 در مقدار انرژی مصرفی، بیانگر کاهش انرژی مصرفی نسبت به روش های مرسوم در مراجع موجود است، هرچند احتمالا سربار سامانه پیشنهادی نسبت به برخی روش های قبلی افزایش می یابد.
The lower power consumption, larger communication bandwidth, and reduced latency are advantages of optical networks over electrical communications. However, there are challenges in these networks, such as routing and connectivity issues, which result in increased network size and wastage. As networks become more complex and larger, building on-chip networks brings problems like communication costs between components and the likelihood of unpredictable failures in communication circuits. Therefore, providing an error-tolerant routing algorithm plays a crucial role in the development of on-chip network architecture. In this article, an adaptive fault-tolerant routing algorithm will be presented, whose main objective is to create the ability to handle a reasonable number of faults without disrupting the healthy nodes in the network. The simulation results of message delay in the proposed method show a gradient norm equal to 1.1691E-5 and μ = 1E-8 for epoch=280, demonstrating its capability to reduce delay in the network. A very slight change in message delay in evaluating the proposed method also indicates the acceptability of the proposed method. Moreover, the presence of a gradient of 1.527E-3 and μ = 1E-7 for epoch=350 in the energy consumption value indicates a reduction in energy consumption compared to conventional methods in existing references, although the proposed system may incur additional overhead compared to some previous methods.
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[3] S. M. A. Zanjani and M. Parvizi, “Design and Simulation of a Bulk Driven Operational Trans-Conductance Amplifier Based on CNTFET Technology,” Journal of Intelligent Procedures in Electrical Technology, vol. 12, no. 45, pp. 63-74, 2021, dor: 20.1001.1.23223871.1400.12.1.5.1 (in Persian).
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[8] S. Zarmehi, M. Daneshvar Farzanegan and A. Avokh, “A New Algorithm for Link Scheduling in MIMO Wireless Mesh Networks with Various Interference Condition by Ant Colony Algorithm,” Journal of Intelligent Procedures in Electrical Technology , vol. 15, no. 58, pp. 31-44, 2024, dor: 20.1001.1.23223871.1403.15.58.3.4 (in Persian).
[9] B. S. Heera, Y. N. Singh and A. Sharma, "Congestion-Aware Dynamic RMCSA Algorithm for Spatially Multiplexed Elastic Optical Networks," International Conference on Optical Network Design and Modeling (ONDM), Coimbra, Portugal, 2023, pp. 1-6.
[10] J. Zhang and E. Yeh, “Congestion-aware routing and content placement in elastic cache networks.” arXiv, vol. 2303.01648, 2023.
[11] J. Oladipo, M. C. du Plessis and T. Gibbon, “Congestion aware ant colony optimisation algorithm for routing and spectrum assignment in flexi-grid optical burst switching networks.” Photonic Network Communications, vol. 45, no. 2, pp. 67-78, 2023, doi: 10.1007/s11107-023-00993-3.
[12] C. Marcon, T. Webber and A. A. Susin, “Models of computation for NoC mapping: Timing and energy saving awareness,” Microelectronics Journal, vol. 60, pp. 129-143, 2017, doi: 10.1016/j.mejo.2016.09.005.
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[14] J. Sepulveda, D. Flórez, V. Immler, G. Gogniat and G. Sigl, “Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs,” Microprocessors and Microsystems, vol. 50, pp. 164-174, 2017, doi:10.1016/j.micpro.2017.03.002.
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[17] J. Wu, "A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model," in IEEE Transactions on Computers, vol. 52, no. 9, pp. 1154-1169, Sept. 2003, doi: 10.1109/TC.2003.1228511.
[18] J. Wu and Z. Jiang, “On Constructing the Minimum Orthogonal Convex Polygon for the Fault-Tolerant Routing in 2-D Faulty Meshesl,” IEEE Trans. on Reliability, vol. 54, no. 3, pp. 449-458, 2015. doi: 10.1109/TR.2005.853039.
[19] M. R. Casu and P. Giaccone, “Power-performance assessment of different DVFS control policies in NoCs,” Journal of Parallel and Distributed Computing, vol. 109, pp. 193-207, 2017, doi: 10.1016/j.jpdc.2017.06.004.
[20] R. Bishnoi, “Hybrid fault tolerant routing algorithm in NoC,” Perspectives in Science, vol. 8, pp. 586-588, 2016, doi: 10.1016/j.pisc.2016.06.028.
_||_[1] M. R. Hemmati, M. Dolatshahi and A. Mehrbod, "Increasing the efficiency of NOC routing algorithms based on fault tolerance measurement method," International Young Engineers Forum (YEF-ECE), Costa da Caparica, Portugal, 2018, pp. 31-38, doi: 10.1109/YEF-ECE.2018.8368935.
[2] A. Rezaei and S. M.A. Zanjani, “Design and Analysis of 2 Memristor-Based Nonvolatile SRAMCells,” Journal of Novel Researches on Electrical Power, vol. 9, no. 2, pp. 47-56, 2020, dor: 20.1001.1. 23222468.1399.9.2.6.6 (in Persian).
[3] S. M. A. Zanjani and M. Parvizi, “Design and Simulation of a Bulk Driven Operational Trans-Conductance Amplifier Based on CNTFET Technology,” Journal of Intelligent Procedures in Electrical Technology, vol. 12, no. 45, pp. 63-74, 2021, dor: 20.1001.1.23223871.1400.12.1.5.1 (in Persian).
[4] L. Benini and G. deMicheli, “Networks-on-Chip: A New Paradigm for System on Chip Design,” Design Automation and Test in Europe (DATE’02), vol. 35, no. 1, pp. 70-78, 2015, doi: 10.1109/DATE.2002.998307.
[5] A. B. Gabis and M. Koudil, “NoC routing protocols – objective-based classification,” Journal of Systems Architecture, vol. 66–67, pp. 14-32, 2016, doi: 10.1016/j.sysarc.2016.04.011.
[6] S. Raja, J. Logeshwaran, S. Venkatasubramanian, M. Jayalakshmi, N. Rajeswari, N. G. Olaiya and W. D. Mammo, “OCHSA: designing energy-efficient lifetime-aware leisure degree adaptive routing protocol with optimal cluster head selection for 5G communication network disaster management,” Scientific Programming,vol. 2022, Article ID : 5424356, 2022, doi: 10.1155/2022/5424356.
[7] F. Fazli, M. Mansubbassiri and F. Babazadeh, “A-RPL: Routing Algorithm with the Ability to Support Mobility in Internet of Things Networks,” vol. 13, no. 50, pp. 11-32, doi: 10.30495/jce.2023.1975641.1183 (in Persian).
[8] S. Zarmehi, M. Daneshvar Farzanegan and A. Avokh, “A New Algorithm for Link Scheduling in MIMO Wireless Mesh Networks with Various Interference Condition by Ant Colony Algorithm,” Journal of Intelligent Procedures in Electrical Technology , vol. 15, no. 58, pp. 31-44, 2024, dor: 20.1001.1.23223871.1403.15.58.3.4 (in Persian).
[9] B. S. Heera, Y. N. Singh and A. Sharma, "Congestion-Aware Dynamic RMCSA Algorithm for Spatially Multiplexed Elastic Optical Networks," International Conference on Optical Network Design and Modeling (ONDM), Coimbra, Portugal, 2023, pp. 1-6.
[10] J. Zhang and E. Yeh, “Congestion-aware routing and content placement in elastic cache networks.” arXiv, vol. 2303.01648, 2023.
[11] J. Oladipo, M. C. du Plessis and T. Gibbon, “Congestion aware ant colony optimisation algorithm for routing and spectrum assignment in flexi-grid optical burst switching networks.” Photonic Network Communications, vol. 45, no. 2, pp. 67-78, 2023, doi: 10.1007/s11107-023-00993-3.
[12] C. Marcon, T. Webber and A. A. Susin, “Models of computation for NoC mapping: Timing and energy saving awareness,” Microelectronics Journal, vol. 60, pp. 129-143, 2017, doi: 10.1016/j.mejo.2016.09.005.
[13] C.-H. Huang, C.-Y. Wang and P.-A. Hsiung, “Elastic superposition task mapping for NoC-based reconfigurable systems,” Microprocessors and Microsystems, vol. 51, pp. 297-312, 2017, doi: 10.1016/j.micpro.2016.12.002.
[14] J. Sepulveda, D. Flórez, V. Immler, G. Gogniat and G. Sigl, “Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs,” Microprocessors and Microsystems, vol. 50, pp. 164-174, 2017, doi:10.1016/j.micpro.2017.03.002.
[15] S. Wamakulasuriya and T. M. Pinkston, “Characterization of Deadlocks in Interconnection Networks,” in Proc. of the international Conference on Parallel Processing, 2015, pp. 80-86, doi:10.1109/IPPS.1997.580852.
[16] Ge-Ming Chiu, "The odd-even turn model for adaptive routing," in IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000, doi: 10.1109/71.877831.
[17] J. Wu, "A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model," in IEEE Transactions on Computers, vol. 52, no. 9, pp. 1154-1169, Sept. 2003, doi: 10.1109/TC.2003.1228511.
[18] J. Wu and Z. Jiang, “On Constructing the Minimum Orthogonal Convex Polygon for the Fault-Tolerant Routing in 2-D Faulty Meshesl,” IEEE Trans. on Reliability, vol. 54, no. 3, pp. 449-458, 2015. doi: 10.1109/TR.2005.853039.
[19] M. R. Casu and P. Giaccone, “Power-performance assessment of different DVFS control policies in NoCs,” Journal of Parallel and Distributed Computing, vol. 109, pp. 193-207, 2017, doi: 10.1016/j.jpdc.2017.06.004.
[20] R. Bishnoi, “Hybrid fault tolerant routing algorithm in NoC,” Perspectives in Science, vol. 8, pp. 586-588, 2016, doi: 10.1016/j.pisc.2016.06.028.