بررسی رفتار نشست ولتاژ کنترل در مدارهای حلقه قفل فاز با در نظر گرفتن اثرات غیر ایده آل و حساسیت به تغییرات المانهای مدار
محورهای موضوعی : مهندسی الکترونیک
ریحانه نظرآقایی
1
(گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران)
عبدالرسول قاسمی
2
(استادیار گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران)
نجمه چراغی شیرازی
3
(استادیار گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران)
کلید واژه: اسیلاتور کنترل شده با ولتاژ, حلقه قفل فاز, آشکارساز فاز,
چکیده مقاله :
در این مقاله به بررسی جامعی از چگونگی رفتار نشست ولتاژ کنترل در اسیلاتورهای کنترل شده با ولتاژ(VCO) با در نظر گرفتن همه عوامل غیرایده‌آل در مدارهای حلقه قفل فاز پرداخته شده است. همچنین ساختارهای مختلف آشکار ساز فاز و تاثیر آنها بر روی سرعت قفل شدن مدار حلقه قفل فاز، ریپل ولتاژ کنترل و محدوده فرکانسی قفل با هم مقایسه خواهد شد. سه مدار حلقه قفل فاز با آشکاز فاز XOR، آشکارساز RS-FF و آشکارساز فاز دینامیکی در این مقاله بررسی شدند. شبیه سازیها در تکنولوژی 0.18µm-CMOS و با منبع تغذیه 1.8v انجام شد. نتایج شبیه سازی نشان می‌دهد محدوده عمل مدار حلقه قفل فاز شامل آشکار فاز دینامیکی با مدار پمپ بار نسبت به اثرات غیرایده‌آل نسبت به مدار حلقه قفل فاز شامل آشکار فاز XOR و مدار حلقه قفل فاز شامل آشکار فاز RS-FF ریپل کمتری دارد. واژه های کلیدی :حلقه قفل فاز، آشکارساز فاز، اسیلاتور کنترل شده با ولتاژ
This paper comprehensively investigates how the control voltage settles in Voltage Controlled Oscillators (VCO) by considering all non-ideal factors in phase lock loop circuits. Also, the different structures of the phase detector and their effect on the locking speed of the phase-locking loop circuit, the control voltage ripple and the locking frequency range will be compared. Three phase locked loop circuits with XOR detector, RS-FF detector and dynamic phase detector were investigated in this paper. The simulations were performed on 0.18 µm-CMOS technology with a 1.8V power supply. The simulation results show that the operating range of the phase-locked loop circuit including dynamic phase detector with charge pump circuit has less ripple for the non-ideal effects compared to the phase-locked loop circuit including XOR phase detector and the phase-locked loop circuit including RS-FF phase detector. of the phase-locked loop circuit including dynamic phase detector is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, frequency range is 0.284-3.33GHz, power consumption is 2.86mW and phase noise is -118.8dBc/Hz.
[1] B. Razavi, RF Microelectronics, NJ:Prentice-Hall, 1997.
[2] A. Hajimiri and T.H. Lee, The Design of Low Noise Oscillators, Springer Science & Business Media, 1999.
[3] M. H. Chou and S. I. Liu, "A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 11, pp. 2474-2478, Nov. 2020, doi: 10.1109/TVLSI.2020.3014885.
[4] P. Kanjiya, V. Khadkikar and M. S. E. Moursi, "Obtaining Performance of Type-3 Phase-Locked Loop Without Compromising the Benefits of Type-2 Control System," in IEEE Transactions on Power Electronics, vol. 33, no. 2, pp. 1788-1796, Feb. 2018, doi: 10.1109/TPEL.2017.2686440.
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[6] S. Golestan, J. M. Guerrero and J. C. Vasquez, "DC-Offset Rejection in Phase-Locked Loops: A Novel Approach," in IEEE Transactions on Industrial Electronics, vol. 63, no. 8, pp. 4942-4946, Aug. 2016, doi: 10.1109/TIE.2016.2546219.
[7] A. Elshazly, R. Inti, B. Young and P. K. Hanumolu, "Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops," in IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1416-1428, June 2013, doi: 10.1109/JSSC.2013.2254552.
[8] T. Yoshimura, "Study of Injection Pulling of Oscillators in Phase-Locked Loops," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 321-332, Feb. 2021, doi: 10.1109/TVLSI.2020.3037895.
[9] L. Zhang, A. Daryoush, A. Poddar and U. Rohde, "Oscillator phase noise reduction using self-injection locked and phase locked loop (SILPLL)," IEEE International Frequency Control Symposium (FCS), 2014, pp. 1-4, doi: 10.1109/FCS.2014.6860007.
[10] A. Godave, P. Choudhari and A. Jadhav, "Comparison and Simulation of Analog and Digital Phase Locked Loop," International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018, pp. 1-4, doi: 10.1109/ICCCNT.2018.8494198.
[11] W. H. Chiu, Y. H. Huang and T. -H. Lin, "A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1137-1149, June 2010, doi: 10.1109/JSSC.2010.2046235.
[12] N. C. Shirazi and R. Hamzehyan, " Evaluation of phase noise performance of voltage-controlled integrated inductors and active inductors with 0.18 µm CMOS technology," Journal of Communication Engineering., vol. 7,no.25, pp. 31-38, 2017 (in Persian).
[13] N. C. Shirazi , E. A. Jahromi and R. Hamzehyan, " Investigating the performance of active vector and inductor capacitors in the resonant circuit of integrated VCOs with 0.18 µmCMOS technology," Journal of Communication Engineering., vol. 7,no.26, pp. 31-38, 2017 (in Persian).
[14] R. Magerramov and V. Zaitsev, "Research Parameters of a PLL System Based on Active and Passive Low-Pass Filter in 0.25-um CMOS Technology," IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus), 2021, pp. 2587-2589, doi: 10.1109/ElConRus51938.2021.9396668.
[15] W. C. Lai, "Dual Band Current Reusing VCO with Loop Filter and Sigma-Delta Modulators for PLL Applications," 2021 International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME), 2021, pp. 1-4, doi: 10.1109/ICECCME52200.2021.9591145.
[16] T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester and D. Blaauw, "A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 50-65, Jan. 2018, doi: 10.1109/JSSC.2017.2776313.
[17] Y. Ho and C. Yao, "A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1984-1992, May 2016, doi: 10.1109/TVLSI.2015.2470545.
[18] I. Lee, K. Zeng and S. Liu, "A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 9, pp. 547-551, Sept. 2013, doi: 10.1109/TCSII.2013.2268640.
[19] S. Rong, J. Yin, and H. C. Luong, “A 0.05- to 10-GHz, 19-to 22-GHz, and 38-to 44-GHz frequency synthesizer for software-defined radios in 0.13µm CMOS process,” IEEE Trans. Circuits Syst. II, Exp.Briefs,vol. 63, no. 1, pp. 109–113, Jan. 2016, doi: 10.1109/TCSII.2015.2482467.
[20] S.Y. Yang, W.Z. Chen, and T.-Y. Lu, "A 7.1 mW, 10 GHz all digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology, " IEEE J. Solid-State Circuits, vol. 45, no. 3,pp. 578–586, Mar. 2010, doi: 10.1109/JSSC.2009.2039530.
[21] S. Huang, S. Liu, J. Hu, R. Wang and Z. Zhu, "A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS," in IEEE Microwave and Wireless Components Letters, vol. 29, no. 6, pp. 397-399, June 2019, doi: 10.1109/LMWC.2019.2909656.
[22] J. Borremans, K. Vengattaramane, V. Giannini, B. Debaillie, W. Van Thillo and J. Craninckx, "A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS," in IEEE Journal of Solid-State Circuits, vol. 45, no. 10, pp. 2116-2129, Oct. 2010, doi: 10.1109/JSSC.2010.2063630.
[23] W. Deng, S. Hara, A. Musa, K. Okada and A. Matsuzawa, "A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios," in IEEE Journal of Solid-State Circuits, vol. 49, no. 9, pp. 1984-1994, Sept. 2014, doi: 10.1109/JSSC.2014.2334392.
_||_[1] B. Razavi, RF Microelectronics, NJ:Prentice-Hall, 1997.
[2] A. Hajimiri and T.H. Lee, The Design of Low Noise Oscillators, Springer Science & Business Media, 1999.
[3] M. H. Chou and S. I. Liu, "A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 11, pp. 2474-2478, Nov. 2020, doi: 10.1109/TVLSI.2020.3014885.
[4] P. Kanjiya, V. Khadkikar and M. S. E. Moursi, "Obtaining Performance of Type-3 Phase-Locked Loop Without Compromising the Benefits of Type-2 Control System," in IEEE Transactions on Power Electronics, vol. 33, no. 2, pp. 1788-1796, Feb. 2018, doi: 10.1109/TPEL.2017.2686440.
[5] A. Mann, A. Karalkar, L. He and M. Jones, "The design of a low-power low-noise phase lock loop," International Symposium on Quality Electronic Design (ISQED), 2010, pp. 528-531, doi: 10.1109/ISQED.2010.5450522.
[6] S. Golestan, J. M. Guerrero and J. C. Vasquez, "DC-Offset Rejection in Phase-Locked Loops: A Novel Approach," in IEEE Transactions on Industrial Electronics, vol. 63, no. 8, pp. 4942-4946, Aug. 2016, doi: 10.1109/TIE.2016.2546219.
[7] A. Elshazly, R. Inti, B. Young and P. K. Hanumolu, "Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops," in IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1416-1428, June 2013, doi: 10.1109/JSSC.2013.2254552.
[8] T. Yoshimura, "Study of Injection Pulling of Oscillators in Phase-Locked Loops," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 321-332, Feb. 2021, doi: 10.1109/TVLSI.2020.3037895.
[9] L. Zhang, A. Daryoush, A. Poddar and U. Rohde, "Oscillator phase noise reduction using self-injection locked and phase locked loop (SILPLL)," IEEE International Frequency Control Symposium (FCS), 2014, pp. 1-4, doi: 10.1109/FCS.2014.6860007.
[10] A. Godave, P. Choudhari and A. Jadhav, "Comparison and Simulation of Analog and Digital Phase Locked Loop," International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018, pp. 1-4, doi: 10.1109/ICCCNT.2018.8494198.
[11] W. H. Chiu, Y. H. Huang and T. -H. Lin, "A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1137-1149, June 2010, doi: 10.1109/JSSC.2010.2046235.
[12] N. C. Shirazi and R. Hamzehyan, " Evaluation of phase noise performance of voltage-controlled integrated inductors and active inductors with 0.18 µm CMOS technology," Journal of Communication Engineering., vol. 7,no.25, pp. 31-38, 2017 (in Persian).
[13] N. C. Shirazi , E. A. Jahromi and R. Hamzehyan, " Investigating the performance of active vector and inductor capacitors in the resonant circuit of integrated VCOs with 0.18 µmCMOS technology," Journal of Communication Engineering., vol. 7,no.26, pp. 31-38, 2017 (in Persian).
[14] R. Magerramov and V. Zaitsev, "Research Parameters of a PLL System Based on Active and Passive Low-Pass Filter in 0.25-um CMOS Technology," IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus), 2021, pp. 2587-2589, doi: 10.1109/ElConRus51938.2021.9396668.
[15] W. C. Lai, "Dual Band Current Reusing VCO with Loop Filter and Sigma-Delta Modulators for PLL Applications," 2021 International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME), 2021, pp. 1-4, doi: 10.1109/ICECCME52200.2021.9591145.
[16] T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester and D. Blaauw, "A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector," in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 50-65, Jan. 2018, doi: 10.1109/JSSC.2017.2776313.
[17] Y. Ho and C. Yao, "A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1984-1992, May 2016, doi: 10.1109/TVLSI.2015.2470545.
[18] I. Lee, K. Zeng and S. Liu, "A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 9, pp. 547-551, Sept. 2013, doi: 10.1109/TCSII.2013.2268640.
[19] S. Rong, J. Yin, and H. C. Luong, “A 0.05- to 10-GHz, 19-to 22-GHz, and 38-to 44-GHz frequency synthesizer for software-defined radios in 0.13µm CMOS process,” IEEE Trans. Circuits Syst. II, Exp.Briefs,vol. 63, no. 1, pp. 109–113, Jan. 2016, doi: 10.1109/TCSII.2015.2482467.
[20] S.Y. Yang, W.Z. Chen, and T.-Y. Lu, "A 7.1 mW, 10 GHz all digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology, " IEEE J. Solid-State Circuits, vol. 45, no. 3,pp. 578–586, Mar. 2010, doi: 10.1109/JSSC.2009.2039530.
[21] S. Huang, S. Liu, J. Hu, R. Wang and Z. Zhu, "A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS," in IEEE Microwave and Wireless Components Letters, vol. 29, no. 6, pp. 397-399, June 2019, doi: 10.1109/LMWC.2019.2909656.
[22] J. Borremans, K. Vengattaramane, V. Giannini, B. Debaillie, W. Van Thillo and J. Craninckx, "A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS," in IEEE Journal of Solid-State Circuits, vol. 45, no. 10, pp. 2116-2129, Oct. 2010, doi: 10.1109/JSSC.2010.2063630.
[23] W. Deng, S. Hara, A. Musa, K. Okada and A. Matsuzawa, "A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios," in IEEE Journal of Solid-State Circuits, vol. 49, no. 9, pp. 1984-1994, Sept. 2014, doi: 10.1109/JSSC.2014.2334392.