یک مبدل کسینوسی گسسته بدون ضرب کننده با استفاده از گیت اکثریت و جمع کننده تقریبی
محورهای موضوعی : مهندسی الکترونیک
الهام اسماعیلی
1
(گروه مهندسی برق، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران)
فرشاد پسران
2
(گروه مهندسی برق، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران)
نبی اله شیری
3
(گروه مهندسی برق، واحد شیراز، دانشگاه آزاد اسلامی، شیراز، ایران)
کلید واژه: DCT بدون ضرب کننده, گیت اکثریت, جمع کننده تقریبی, تبدیل کسینوسی گسسته,
چکیده مقاله :
این مقاله یک جمع‌کننده کامل جدید را با استفاده از محاسبات تقریبی بر اساس مفهوم منطق اکثریت (ML) پیشنهاد می‌کند. مفهوم ML به دلیل مشخصات منحصر به فرد خود برای استفاده در متدولوژی های مختلف بسیار کارآمد و قابل استفاده است و ساختار بنیادی آن گیت های اکثریت 3 ورودی است به طور گسترده در سلول های حساب دیجیتال استفاده شده است. جمع‌کننده پیشنهادی مبتنی بر ML با توان کم، تأخیر کم و محصول تأخیر کم توان (PDP) کار می کند. فناوری ترانزیستور اثر میدانی نانولوله کربنی (CNTFET) توان FA را کاهش می‌دهد و مشکل نوسان با تکنیک آستانه دینامیکی (DT) حل می‌شود. مدار پیشنهادی با دو پیکربندی جمع کننده کامل تقریبی مقایسه شده است. معماری های مورد نظر با استفاده از معیارهای سخت افزاری از جمله تاخیر، توان، PDP و میانگین فاصله خطای نرمال شده (MNED) علاوه بر معیارهای خطا ارزیابی می شوند. در مقایسه با ادبیات، طرح پیشنهادی عملکرد برتری دارد. علاوه بر این، FA پیشنهادی در طراحی تبدیل کسینوس گسسته بدون ضرب (DCT) تعبیه شده است، که یک مدار مناسب برای سیستم‌های ادغام در مقیاس بسیار بزرگ (VLSI) و پردازنده‌های سیگنال دیجیتال (DSPs) است. نتایج اجرای DCT کارایی FA پیشنهادی را تایید می کند.
This paper proposes a new approximate full adder (FA) based on the majority logic (ML) concept. The fundamental structure of the ML concept is a 3-input majority voter and is widely utilized in digital arithmetic cells. The ML-based proposed FA works at low power, small delay, and low power-delay-product (PDP). The carbon nanotube field-effect transistor (CNTFET) technology lowers the FA power, while the gate diffusion input (GDI) technique is used as the main technique. The swing issue of the GDI technique is resolved by the dynamic threshold (DT) technique. Compared with its exact circuit, the proposed FA saves 2 majority gates, 3 inverters, and a 4.02 ns delay. In the proposed FA, the PDP is improved by 53.73%. The product of the PDP and the normalized mean error distance (NMED) is called PDPE, and in the presented FA, it is reduced by 9.50%. Moreover, the proposed FA is embedded into a multiplier-less discrete cosine transform (DCT) design, which is an appropriate circuit for very large-scale integration (VLSI) systems. The 8-input DCT architecture consumed 2.2321 mW of power for each DCT operation. Also, the circuit has better performance in terms of PDP-area-product (PDAP). The results of DCT implementations confirm the efficiency of the FA.
[1] M. Rafiee, N.Shiri and A.Sadeghi, “High-performance 1-bit full adder with excellent driving capability for multista structures,’’ IEEE Embedded Syst Lett., vol. 14, no. 1, pp. 47-50, 2021, doi: 10.1109/LES..3108474.
[2] N. Shiri, A.Sadeghi,M. Rafiee and M.Bigonah “SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits,” Int. J. Circ. Theor. Appl.;pp.1-26, 2022, doi:10.1002/cta.3251.
[3] S. Ansari, H. Jiang, B.Cockburn and J.Han, “Low-power approximate multipliers using encoded partial products and approximate compressors,’’IEEE J Emerg Sel Top Circ Syst., vol. 8, no. 3, pp. 404-416, 2018, doi:10.1109/JETCAS.2832204.
[4] J. Deng and W. H-SP, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the Intrinsic Channel Region,’’ IEEE Trans Electron Dev., vol. 54, no. 12, pp. 3186-3194, 2007, doi:10.1109/TED.909030.
[5] Z. Chu, C. Shang, T. Zhang, Y. Xia, L. Wang and W. Liu, “Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits, ” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 12, pp. 1827-1839, Dec. 2022, doi: 10.1109/TVLSI.2022.3210252.
[6] T. Zhang, W. Liu, E. McLarnon, M. O'Neill and F. Lombardi, "Design of Majority Logic (ML) Based Approximate Full Adders, ” IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8350962.
[7] C. Labrado, H. Thapliyal and F. Lombardi, “Design of majority logic based approximate arithmetic circuits, ” IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050819.
[8] E. Esmaeili, F.Pesaran and N.Shiri. “A high-efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression’’ Int. J. Circ.Theor.Appl. vol. 51, no. 3, pp. 1‐24, 2023, doi:10.1002/cta.3551.
[9] T. Rashedzadeh, S.M. Riazi and N. Cheraghi Shirazi, “Analysis of effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25–36, July 2021, (in persian).
[10] H. Arfavi, SM. Riazi, and R. Hamzehyan, “Evaluation of temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method,” Journal of Southern Communication Engineering, June 2023, doi: 10.30495/jce.2023.1973764.1197, (in persian).
[11] M. Sayyaf, A. Ghasemi and R. Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, 2022, doi: 10.30495/jce.2022.692834, (in persian).
[12] A. Sadeghi, N. Shiri, and M. Rafiee, M.Tahghigh. “An efficient counter-based Wallace-tree multiplierwith hybrid full adder core for image blending,” Front Inform Technol Electron Eng, Vol. 23, PP.950–965, 2022, https://doi.org/10.1631/FITEE.2100432.
[13] F. M. Bayer and R. J. Cintra, “Image Compression via a Fast DCT Approximation,” in IEEE Latin America Transactions, vol. 8, no. 6, pp. 708-713, Dec. 2010, doi: 10.1109/TLA.2010.5688099.
[14] S. Bouguezel, M. O. Ahmad and M. N. S. Swamy, “A novel transform for image compression,” IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, USA, 2010, pp. 509-512, doi: 10.1109/MWSCAS.2010.5548745.
[15] M. Jridi, A. Alfalou and P. K. Meher, “A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT, ” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 2, pp. 449-457, Feb. 2015, doi: 10.1109/TCSI.2014.2360763.
[16] R. J. Cintra and F. M. Bayer, “A DCT Approximation for Image Compression, ” in IEEE Signal Processing Letters, vol. 18, no. 10, pp. 579-582, Oct. 2011, doi: 10.1109/LSP.2011.2163394.
[17] U S. Potluri, A .Madanayake, R J. Cintra, F M. Bayer and N. Rajapaksha, “Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing,” Meas. Sci. Technol., vol. 23, p. 114003, 2012, doi: 10.1088/0957-0233/23/11/114003.
[18] A. Sadeghi, N. Shiri, and M. Rafiee, “High-Efficient, Ultra-Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications,” Circuits Syst Signal Process , vol. 39, pp. 6247–6275, 2020, doi: 10.1007/s00034-020-01459-x.
[19] A. Sadeghi., et al.: “Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell,’’ IET Circuits Devices Syst. vol. 16, no. 1, pp. 1-24, 2022, doi: 10.1049/cds2.12117.
[20] H. Cho and E. E. Swartzlander, “Adder and Multiplier Design in Quantum-Dot Cellular Automata, ” in IEEE Transactions on Computers, vol. 58, no. 6, pp. 721-727, June 2009, doi: 10.1109/TC.2009.21.
[21] S. Bouguezel, M.O. Ahmad and M.N.S. Swamy, “Low-complexity 8× 8 transform for image compression,” Electron. Lett., vol. 44, no. 21, pp. 1249–1250, 2008, doi: 10.1049/el:20082239.
[22] Y. -H. Chen, T. -Y. Chang and C. -Y. Li, “High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 709-714, April 2011, doi: 10.1109/TVLSI.2009.2037968.
[23] N. R. Konijeti, J. V. R. Ravindra and P. Yagateela, “Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology,” European Modelling Symposium, Manchester, UK, 2013, pp. 697-700, doi: 10.1109/EMS.2013.117.
[24] G. Ramana Murthy, C. Senthilpari, P. Velrajkumr and L.T. Sze, “A novel design of multiplexer based full-adder cell for power and propagation delay optimization,” Journal of Engineering Science and Technology, vol. 8, no. 6, pp. 764–777. 2013.
[25] S. Verma, D. Kumar and G. K. Marwah, “New High Performance 1-Bit Full Adder Using Domino Logic,” International Conference on Computational Intelligence and Communication Networks, Bhopal, India, 2014, pp. 961-965, doi: 10.1109/CICN.2014.203.
[26] M. Mirzaei and S. Mohammadi, “Process variation-aware approximate full adders for imprecision-tolerant applications,” Computers & Electrical Engineering, vol. 87, p. 106761, 2020, doi: 10.1016/j.compeleceng.2020.106761.
[27] M. C. Parameshwara and N. Maroof, “An Area-EfficientMajority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications,” Circuits, Systems, and Signal Processing, vol. 41, pp. 4977–4997, 2022, doi: 10.1007/s00034-022-02014-6.
_||_[1] M. Rafiee, N.Shiri and A.Sadeghi, “High-performance 1-bit full adder with excellent driving capability for multista structures,’’ IEEE Embedded Syst Lett., vol. 14, no. 1, pp. 47-50, 2021, doi: 10.1109/LES..3108474.
[2] N. Shiri, A.Sadeghi,M. Rafiee and M.Bigonah “SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits,” Int. J. Circ. Theor. Appl.;pp.1-26, 2022, doi:10.1002/cta.3251.
[3] S. Ansari, H. Jiang, B.Cockburn and J.Han, “Low-power approximate multipliers using encoded partial products and approximate compressors,’’IEEE J Emerg Sel Top Circ Syst., vol. 8, no. 3, pp. 404-416, 2018, doi:10.1109/JETCAS.2832204.
[4] J. Deng and W. H-SP, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the Intrinsic Channel Region,’’ IEEE Trans Electron Dev., vol. 54, no. 12, pp. 3186-3194, 2007, doi:10.1109/TED.909030.
[5] Z. Chu, C. Shang, T. Zhang, Y. Xia, L. Wang and W. Liu, “Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits, ” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 12, pp. 1827-1839, Dec. 2022, doi: 10.1109/TVLSI.2022.3210252.
[6] T. Zhang, W. Liu, E. McLarnon, M. O'Neill and F. Lombardi, "Design of Majority Logic (ML) Based Approximate Full Adders, ” IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8350962.
[7] C. Labrado, H. Thapliyal and F. Lombardi, “Design of majority logic based approximate arithmetic circuits, ” IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050819.
[8] E. Esmaeili, F.Pesaran and N.Shiri. “A high-efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression’’ Int. J. Circ.Theor.Appl. vol. 51, no. 3, pp. 1‐24, 2023, doi:10.1002/cta.3551.
[9] T. Rashedzadeh, S.M. Riazi and N. Cheraghi Shirazi, “Analysis of effect of changes of FINs Architectural on FINFET Drain current and on Average Power Dissipation and Propagation Delay in the Hybrid-CMOS full adder,” Journal of Southern Communication Engineering, vol. 10, no. 40, pp. 25–36, July 2021, (in persian).
[10] H. Arfavi, SM. Riazi, and R. Hamzehyan, “Evaluation of temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method,” Journal of Southern Communication Engineering, June 2023, doi: 10.30495/jce.2023.1973764.1197, (in persian).
[11] M. Sayyaf, A. Ghasemi and R. Hamzehyan, “Design of Low Power Single-Bit Full-Adder Cell Based on Pass-Transistor Logic,” Journal of Southern Communication Engineering, 2022, doi: 10.30495/jce.2022.692834, (in persian).
[12] A. Sadeghi, N. Shiri, and M. Rafiee, M.Tahghigh. “An efficient counter-based Wallace-tree multiplierwith hybrid full adder core for image blending,” Front Inform Technol Electron Eng, Vol. 23, PP.950–965, 2022, https://doi.org/10.1631/FITEE.2100432.
[13] F. M. Bayer and R. J. Cintra, “Image Compression via a Fast DCT Approximation,” in IEEE Latin America Transactions, vol. 8, no. 6, pp. 708-713, Dec. 2010, doi: 10.1109/TLA.2010.5688099.
[14] S. Bouguezel, M. O. Ahmad and M. N. S. Swamy, “A novel transform for image compression,” IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, USA, 2010, pp. 509-512, doi: 10.1109/MWSCAS.2010.5548745.
[15] M. Jridi, A. Alfalou and P. K. Meher, “A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT, ” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 2, pp. 449-457, Feb. 2015, doi: 10.1109/TCSI.2014.2360763.
[16] R. J. Cintra and F. M. Bayer, “A DCT Approximation for Image Compression, ” in IEEE Signal Processing Letters, vol. 18, no. 10, pp. 579-582, Oct. 2011, doi: 10.1109/LSP.2011.2163394.
[17] U S. Potluri, A .Madanayake, R J. Cintra, F M. Bayer and N. Rajapaksha, “Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing,” Meas. Sci. Technol., vol. 23, p. 114003, 2012, doi: 10.1088/0957-0233/23/11/114003.
[18] A. Sadeghi, N. Shiri, and M. Rafiee, “High-Efficient, Ultra-Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications,” Circuits Syst Signal Process , vol. 39, pp. 6247–6275, 2020, doi: 10.1007/s00034-020-01459-x.
[19] A. Sadeghi., et al.: “Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell,’’ IET Circuits Devices Syst. vol. 16, no. 1, pp. 1-24, 2022, doi: 10.1049/cds2.12117.
[20] H. Cho and E. E. Swartzlander, “Adder and Multiplier Design in Quantum-Dot Cellular Automata, ” in IEEE Transactions on Computers, vol. 58, no. 6, pp. 721-727, June 2009, doi: 10.1109/TC.2009.21.
[21] S. Bouguezel, M.O. Ahmad and M.N.S. Swamy, “Low-complexity 8× 8 transform for image compression,” Electron. Lett., vol. 44, no. 21, pp. 1249–1250, 2008, doi: 10.1049/el:20082239.
[22] Y. -H. Chen, T. -Y. Chang and C. -Y. Li, “High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 709-714, April 2011, doi: 10.1109/TVLSI.2009.2037968.
[23] N. R. Konijeti, J. V. R. Ravindra and P. Yagateela, “Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology,” European Modelling Symposium, Manchester, UK, 2013, pp. 697-700, doi: 10.1109/EMS.2013.117.
[24] G. Ramana Murthy, C. Senthilpari, P. Velrajkumr and L.T. Sze, “A novel design of multiplexer based full-adder cell for power and propagation delay optimization,” Journal of Engineering Science and Technology, vol. 8, no. 6, pp. 764–777. 2013.
[25] S. Verma, D. Kumar and G. K. Marwah, “New High Performance 1-Bit Full Adder Using Domino Logic,” International Conference on Computational Intelligence and Communication Networks, Bhopal, India, 2014, pp. 961-965, doi: 10.1109/CICN.2014.203.
[26] M. Mirzaei and S. Mohammadi, “Process variation-aware approximate full adders for imprecision-tolerant applications,” Computers & Electrical Engineering, vol. 87, p. 106761, 2020, doi: 10.1016/j.compeleceng.2020.106761.
[27] M. C. Parameshwara and N. Maroof, “An Area-EfficientMajority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications,” Circuits, Systems, and Signal Processing, vol. 41, pp. 4977–4997, 2022, doi: 10.1007/s00034-022-02014-6.