بهبود طراحی جمع کننده با استفاده از ترانزیستورهایFinFET
محورهای موضوعی : مجله فناوری اطلاعات در طراحی مهندسیعلی اصغر تاج آبادی 1 * , مهدیه اسلامی 2 , مهدی جعفری شهباز زاده 3
1 - دانشگاه آزاد اسلامی واحد کرمان
2 - دانشگاه آزاد اسلامی واحد کرمان
3 - دانشگاه آزاد اسلامی واحد کرمان
کلید واژه: تمام جمع کننده, فین فت, جریان نشتی, توان مصرفی, تاخیر مدار,
چکیده مقاله :
یکی از بلوک های پرکاربرد در محاسبات کامپیوتری جمع کننده ها هستند و به عنوان بخش عمده ای از پردازنده، برای محاسبه آدرس رجیسترها و سایرعملیات های حسابی عمل می کنند. سرعت جمع کننده تعیین می کند که پردازنده چقدر سریع اجرا خواهد شد و طراحان در حال حاضر بیشتر بر روی سرعت بالا و توان مصرفی پایین متمرکز شدهاند. امروزه با کاهش مقیاس قطعات الکترونیکی در تکنولوژی ساخت، به منظورافزایش تراکم ترانزیستورها در یک تراشه، مشکلاتی مانند اثرات کانال کوتاه، تونل زنی گیت و... پدیدار می شوند که این مشکلات کارایی قطعه را کاهش می دهند. جهت کاهش این اثرات، یکی از ساختارهایی که در تکنولوژی های ساخت بسیار مورد توجه قرار گرفته است، فین فت می باشد که با ایجاد کنترل الکترواستاتیک بهتر بر روی کانال این اثرات را به طورموثر کاهش و سرعت سوییچینگ قطعه را افزایش می دهد. در این پژوهش تمام جمع کننده جدیدی مبتنی برتکنولوژی فین فت ارائه شده است. این تمام جمع کننده با استفاده از دو نیم جمع کننده و10 ترانزیستور طراحی شده است. تمام جمع کننده جدید در نرم افزارHSPICE شبیه سازی شده است. نتایج شبیه سازی کاهش چشمگیر توان مصرفی و Power Delay Product را نشان می دهد.
One of the most commonly used blocks in computer calculations is adders, which serve as a major part of the processor to compute register addresses and other arithmetic operations. The speed of the adder determines how fast the processor will execute, and designers are currently more focused on high speed and low power consumption. Nowadays, with the reduction in the scale of electronic components in manufacturing technology, in order to increase the density of transistors on a chip, issues such as short-channel effects, gate tunneling, and so on arise, which reduce the performance of the component. To reduce these effects, one of the structures that has received significant attention in manufacturing technologies is the FinFET, which effectively reduces these effects and increases the switching speed of the device by providing better electrostatic control over the channel. In this research, a new adder based on FinFET technology has been designed. This full adder is designed using two half adders and 10 transistors. The new full adder has been simulated in the HSPICE software. The simulation results show a significant reduction in power consumption and Power Delay Product.
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