روش جدید در امنیت سیستم های رمزنگاری توسط گیت های نامتوازن
محورهای موضوعی : سامانه های پردازشی و ارتباطی چند رسانه ای هوشمند
سید حمیدرضا موسوی
1
(استادیار، دانشکده مهندسی برق و کامپیوتر، واحد زنجان، دانشگاه آزاد اسلامی، زنجان، ایران.)
مهدی صفائیان
2
(استادیار، دانشکده مهندسی برق و کامپیوتر، واحد هیدج، دانشگاه آزاد اسلامی، زنجان، ایران)
امیر حسن احمدی قلعه
3
(دانش آموخته کارشناسی ارشد، گروه برق، واحد زنجان، دانشگاه آزاد اسلامی، زنجان، ایران)
کلید واژه: حملات تفاضلی توان, گیت, حلقه فاز قفل شده, اندازه گیری توان, استاندارد رمزنگاری پیشرفته,
چکیده مقاله :
امروزه اشتراک اطلاعات و انتقال ایمن آن بین سیستمهای مختلف الکترونیکی ضروری شدهاست. یکی از چالشهای مهم در این زمینه حملات کانال جانبی میباشد که با استفاده از تکنیکهای موجود سعی در بدست آوردن کلید رمزنگاری دارند. هدف از این پژوهش ارائه طرح جدیدی برای مقاوم‌سازی الگوریتم‌های رمزنگاری میباشد. در این طرح با به هم زدن توان مصرفی توسط دو عامل ارتقاء گیت‌های کلیدی و تزریق تصادفی تاخیر در اجرای بخش‌های مختلف از الگوریتم استاندارد رمزنگاری پیشرفتهAES ، میزان مقاومت این سامانه در مقابل حملات تفاضلی توان DPA افزایش یافته است. برای اصلاح گیت XOR از مدلی استفاده شده است که با وجود توان متغیر در زمانهای مختلف عملکردی ثابت و منطقی دارد. ترکیب گیت فوق با تاخیرهای تصادفی که توسط PLL در ناحیه گذرا ساخته می‌شود، مقاومت سیستم را بیشتر بهبود داده است. طرح فوق در تکنولوژی 65nm پیاده شده و نتایج حاصل از شبیه‌سازی در مقابل حملات تفاضلی توان نتایج قابل قبولی را نشان داده است. این طرح تنها هزینه سربار 33 درصد در فضای اشغالی و 25 درصد در توان مصرفی را به دنبال داشته است، و تنها سرعت عملکرد 3 درصد کم شده است در حالی که مقاومت تقریبا دو برابر شده است.
IntroductionNowadays, sharing information in communication systems and computers demands high levels of security. Side channel attacks are mainly considered as a main challenge in cryptographic systems which they are used as attacking techniques to break encrypted devices such as smart cards. The purpose of this research is introducing a new plan for strengthening on-chip encryption algorithms. The proposed plan is based on using Phase-Locked Loop (PLL) and enhanced XOR gate in Advanced Encryption Standard (AES) algorithm. In this approach, by disturbing the power consumption and time of execution for each different round of the algorithm, the encryption algorithm is protected against Differential Power Attacks (DPA). The proposed method has been implemented in TSMC 65nm technology in Cadence and the results show that the algorithm becomes immune against DPA using this method. As overheads, the silicon area and power consumption increased about 33% and 25%, respectively, whereas, the clock rate has been reduced less than 3%. MethodIn modern digital systems, if the data in the systems carries classified information, data encryption is unavoidable. For example, encryption in smart cards, portable electronic devices, mobile phones and remote control devices use encryption systems to deal with unauthorized intruders [1][2]. One of the requirements of today's electronic systems is high speed, low power consumption and information security. The basis of this method is the combination of the two characteristics of delay and power noise injection into the system using gates,ResultsThe comparison of the results in the simulation mode showed that the system has a good resistance against DPA attacksOne of the characteristics that exist to check the ability of retrofitting methods is the amount of hardware overhead and the imposition of additional power in the proposed retrofitting method. To check this issue, the hardware overhead and power consumption of the implemented method are presented in Table (2).DiscussionWith a reasonable number of power diagrams, so that compared to In the previous designs, the number of power diagrams has been almost doubled and the only overhead cost of the system is the increase in the volume of the occupied space by 33% and the power consumption by 20%.
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