Cost-aware Topology Customization of Mesh-based Networks-on-Chip

Subject Areas : Computer Architecture and Digital Systems

Ali Ramezanzad ¹ , Midia Reshadi ²

1 - Department of Computer Engineering Science and Research Branch, Islamic Azad University Tehran, Iran
2 - Department of Computer Engineering Science and Research Branch, Islamic Azad University Tehran, Iran

Received: 2017-04-27 Accepted : 2017-12-14 Published : 2018-05-01

Keywords: long-range link insertion, average latency, Networks-on-chip, power and area consumption,

Abstract :

Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based on grid-like topologies which are also used in application-specific design.The small world network idea recently has been introduced in order to optimize the performance of the Networks-on-chip. Based on this method the architecture will be neither fully customized nor completely regular. Results have shown that by using the long-range links which optimized the network power and performance, the area consumption will exceed. We can derive from this that an acceptable bound on the area consumption should be considered. Based on the restriction of a designer, in this paper we want to present a methodology that will automatically optimize an architecture while at the same time considering the area consumption.

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